DE3471855D1 - Optional single or double clocked latch - Google Patents

Optional single or double clocked latch

Info

Publication number
DE3471855D1
DE3471855D1 DE8484108920T DE3471855T DE3471855D1 DE 3471855 D1 DE3471855 D1 DE 3471855D1 DE 8484108920 T DE8484108920 T DE 8484108920T DE 3471855 T DE3471855 T DE 3471855T DE 3471855 D1 DE3471855 D1 DE 3471855D1
Authority
DE
Germany
Prior art keywords
optional single
clocked latch
double clocked
double
latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8484108920T
Other languages
German (de)
English (en)
Inventor
Donald Burns Kiley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3471855D1 publication Critical patent/DE3471855D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356052—Bistable circuits using additional transistors in the input circuit using pass gates
    • H03K3/35606—Bistable circuits using additional transistors in the input circuit using pass gates with synchronous operation

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Shift Register Type Memory (AREA)
DE8484108920T 1983-08-01 1984-07-27 Optional single or double clocked latch Expired DE3471855D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US51933883A 1983-08-01 1983-08-01

Publications (1)

Publication Number Publication Date
DE3471855D1 true DE3471855D1 (en) 1988-07-07

Family

ID=24067873

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484108920T Expired DE3471855D1 (en) 1983-08-01 1984-07-27 Optional single or double clocked latch

Country Status (3)

Country Link
EP (1) EP0137165B1 (enExample)
JP (1) JPS6049443A (enExample)
DE (1) DE3471855D1 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9417591D0 (en) * 1994-09-01 1994-10-19 Inmos Ltd Scan testable double edge triggered scan cell

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4004170A (en) * 1975-04-29 1977-01-18 International Business Machines Corporation MOSFET latching driver
US3993919A (en) * 1975-06-27 1976-11-23 Ibm Corporation Programmable latch and other circuits for logic arrays

Also Published As

Publication number Publication date
EP0137165A1 (en) 1985-04-17
JPH0325817B2 (enExample) 1991-04-09
JPS6049443A (ja) 1985-03-18
EP0137165B1 (en) 1988-06-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee