JPH0325817B2 - - Google Patents
Info
- Publication number
- JPH0325817B2 JPH0325817B2 JP59078826A JP7882684A JPH0325817B2 JP H0325817 B2 JPH0325817 B2 JP H0325817B2 JP 59078826 A JP59078826 A JP 59078826A JP 7882684 A JP7882684 A JP 7882684A JP H0325817 B2 JPH0325817 B2 JP H0325817B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- circuit
- node
- transistors
- path
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000012360 testing method Methods 0.000 description 14
- 239000003990 capacitor Substances 0.000 description 13
- 230000009977 dual effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318552—Clock circuits details
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
- H03K3/356052—Bistable circuits using additional transistors in the input circuit using pass gates
- H03K3/35606—Bistable circuits using additional transistors in the input circuit using pass gates with synchronous operation
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Shift Register Type Memory (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US51933883A | 1983-08-01 | 1983-08-01 | |
| US519338 | 1983-08-01 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6049443A JPS6049443A (ja) | 1985-03-18 |
| JPH0325817B2 true JPH0325817B2 (enExample) | 1991-04-09 |
Family
ID=24067873
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59078826A Granted JPS6049443A (ja) | 1983-08-01 | 1984-04-20 | ラッチ回路 |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0137165B1 (enExample) |
| JP (1) | JPS6049443A (enExample) |
| DE (1) | DE3471855D1 (enExample) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB9417591D0 (en) * | 1994-09-01 | 1994-10-19 | Inmos Ltd | Scan testable double edge triggered scan cell |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4004170A (en) * | 1975-04-29 | 1977-01-18 | International Business Machines Corporation | MOSFET latching driver |
| US3993919A (en) * | 1975-06-27 | 1976-11-23 | Ibm Corporation | Programmable latch and other circuits for logic arrays |
-
1984
- 1984-04-20 JP JP59078826A patent/JPS6049443A/ja active Granted
- 1984-07-27 EP EP19840108920 patent/EP0137165B1/en not_active Expired
- 1984-07-27 DE DE8484108920T patent/DE3471855D1/de not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6049443A (ja) | 1985-03-18 |
| EP0137165A1 (en) | 1985-04-17 |
| DE3471855D1 (en) | 1988-07-07 |
| EP0137165B1 (en) | 1988-06-01 |
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