JPS604872A - Testing method of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To attain to shorten the testing time of IC, by changing the cycle of an input clock corresponding to the change in the output of IC. CONSTITUTION:In a decimal counter, the application of a clock is not performed to a terminal when an output pattern state changes. In this case, by bringing the comparison of the comparison pattern of an IC tester and the output pattern of IC to judgement prohibition (section 19, 20), influence due to time constant is removed and the cycle of an input clock is made small to shorten a testing time.

Description

DETAILED DESCRIPTION OF THE INVENTION Misfire 811 relates to a testing method for determining the quality of semiconductor integrated circuits.

In the present invention, a test pattern VC is used to determine the acceptability of a semiconductor integrated circuit (hereinafter referred to as an IC) using a general-purpose tester (hereinafter referred to as a tester). Considering the output resistance component of the tester, the human power capacitance component of the tester, and the first delay in the output pattern caused by Characteristically, its purpose is to reduce the testing time of ICs.

That is, the present invention shortens the total period of the input clock by checking whether or not there is a change in the output pattern, and has the advantage that the test time for ICs can be shortened by kneading.

The present invention will be explained in detail using the following r5 diagrams.

FIG. 1K is an example of a counter circuit to which the test pattern of the present invention is applied, and is a decimal counter. L, 2. 3 and 4 are binary free-lag flops. 5 is an ANDφ gate, 6. 71
-J NOR gate, 8c is the output terminal, and 9 is the input terminal 0soh. Figure (aJ
The clock fc vs. 17 for each binary free soge 7
0gl, 2. The C1 child outputs of 3 and 4 are shown in the same figure (1)
), (C), (dJ and (e), and as a result, the output terminal 8 has the following waveforms as shown in (f)rc in the figure.'
A 1FPJ7'l pattern is obtained.

*C2nd[%j(fJ) output terminal 8
The resistance component of and the input capacity of the tester'f! This is a waveform that ignores F81, and the output waveform is as shown in Figure 3 (C1) and has a time delay due to the influence of vibration.

Therefore, in the present invention, the test manual clock signal and comparison pattern shown in FIGS. 3(a) and 3(b) and (c) are constructed taking into account the time delay of the output waveform.

In other words, the period becomes longer at the time when the output changes to the input clock, and the comparison pattern has a fixed prohibition section 19.20 in the output cover turn. We are using the function of a tester to capture the details.

The test pattern according to the present invention has the form shown in FIG. 3, and the period of the input clock shown in FIG. 3(a) is the resistance component of the output terminal 8 and the input capacitance J of the tester! If the time constant is sufficiently larger than the time constant of 1t81 (therefore, r(), the output waveform will be in the form of input clock 1 (l) in the timing chart of FIG. If the period of the input clock is made smaller than this time constant, the tester will make an erroneous judgment. Therefore, it is difficult to shorten the test time by shortening the clock period.

In order to completely eliminate such drawbacks, the present invention does not apply a clock signal when the output pattern of the IC changes, and removes the influence of the comparison pattern of the tester and the output of the IC, and reduces the period of the clock to increase the test time. It shortens the . In this case, a delay occurs due to the cable 19 that constitutes the counter circuit in the IC, but this delay time is longer than the resistance component of the output terminal 8 and the input capacitance 81 f of the tester.
Since the time constant due to fL is long, malfunctions due to delay in the counter circuit will not occur.

The above operation can be applied to shorten the Ic test time. Furthermore, the productivity in the sorting process for determining the quality of the IC for a certain period of time V:Jrc is extremely high, so the industrial efficiency is extremely high.

[Brief explanation of the drawing]

1 (2) is a circuit diagram showing an example of a counter circuit in an IC, FIG. 2 is a timing chart showing an example of a test pattern according to a conventional test method, and FIG. 3 is a timing chart showing an example of the present invention. It is. 1, 2. 3. 4; Binary free-lag frog circuit, 5; AND gate, 6, 7: Noah gate, 8;
Output terminal, 81: Equivalent input capacitance inside the tester, 9; Clock input terminal, lO: Clock waveform, 11, 12, 1
3, 14; Output waveform of binary-free rough "frog, 15; Output waveform, 16; Clock input waveform according to the present invention, 17: Output pattern waveform according to the present invention, 18; IC when clock 16 of the present invention is input. Output waveform of 1
9゜20; Judgment prohibited section

Claims (1)

[Claims] A method for testing a semiconductor integrated circuit characterized by increasing the period of the input clock VC during a period after the output of the semiconductor integrated circuit changes, and shortening the period of the μ input clock during a period when the output does not change.