JPH01176963A - Lsi - Google Patents

Abstract

PURPOSE:To test delay characteristics and the adequacy of an input/output buffer, etc., by providing a delay measuring circuit in addition to an original logic circuit. CONSTITUTION:In a normal state, a test terminal 10 is held at a logic value '0' and then a logic circuit 7 is made effective, but when the LSI is inspected, the terminal 10 is held at a logical value '1' and then tri-state buffers S1, S2, and S3 enter an enabled state to make delay measuring circuits 51, 52, and 53 effective. At this time, tri-state buffers S4, S5, and S6 are masked and a logic circuit 7 becomes ineffective. Then a signal of a prescribed pattern is inputted to an input terminal 21 or 22 or two-way terminal 40 and compared with a signal appearing at an output terminal 31 or 32 or two-way terminal 40 to measure the delay characteristics of the LSI. Further, the signal of the prescribed pattern is passed through the circuits 51, 52, and 53 instead of the complex circuit 7 to easily detect faults of input buffers 61 and 62, etc.

Description

[Detailed description of the invention] flame ■ standing amount The present invention relates to LSIs, and particularly to LSI testing.

Conventional technology In recent years, the degree of integration of LSI has increased with device technology, CAD (Content
+puter aided design) has increased dramatically due to advances in technology. However, despite advances in technology, users who design large-scale, complex, and high-performance LSIs for special purposes without general-purpose use
I-system specifications, that is, logic and circuit design, are forced to become more complex. In addition, the users are forced to complicate the design of LSI inspection specifications, that is, the design of screening test patterns for eliminating defective products at the wafer and package stages, which, combined with the need to shorten the LSI development period, places a heavy burden on them.

On the other hand, the ideal failure detection rate is 100%, and failure detection of external interface elements and external terminals is particularly essential. Therefore, for the user, LS
In I design, especially in its inspection specification design, design of functional test patterns to detect failures of logic elements and patterns at the manufacturing stage due to various factors, and DC/AC test patterns as unit/operation characteristic tests. had the disadvantage of being complicated.

Furthermore, the increase in the number of inspection design man-hours and period for special applications where low-volume, high-mix production is expected has been a major drawback for users designing LSIs.

SUMMARY OF THE INVENTION An object of the present invention is to provide an LSI that can facilitate failure detection of external interface elements and external terminals.

The LSI of the present invention includes a logic circuit, a delay measurement circuit for measuring a delay time due to the logic circuit, an input/output buffer section of the logic circuit, and an input/output buffer section that connects the logic circuit to the input/output buffer section. and a switching means for selectively and electrically switching and connecting the delay measuring circuit and the delay measuring circuit.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a system diagram showing the configuration of an LSI according to the present invention. In FIG. It is configured to include a bidirectional terminal 40.

Further, the LSI according to this embodiment includes a logic circuit 7, delay measurement circuits 51, 52, and 53, and input buffers It and I2.
．． I3 and I4, output buffers 61 and 62, a bidirectional external ink face buffer T, an inverter N, and 3-state buffers St, 82.33.34.35, and S6.

The logic circuit 6 has a logic configuration unique to this LSI. Further, the delay measurement circuits 51, 52 and 53 are respectively standard logic circuits with a standard wiring length, and are used to measure the input/output delay characteristics of this LSI.

The three-state buffers 81 to S6 have enable terminals 1 to 6, respectively, and the enable terminals have a logic value of "1".
”, the 3-state buffer becomes enabled.

In this configuration, when the test terminal 10 is held at a logic value "0" in a normal state, the inverter N enables the three-state buffers S4, 35, and 36, and the logic circuit 7 becomes valid. In this case, input terminal 21
and 22, the output terminals become 31 and 32, and the bidirectional terminal 40 becomes an input or output terminal by switching the Tough Ace buffer T.

On the other hand, when testing an LSI, by holding the test terminal 10 at the logical value "1", the 3-state buffers St, S2... S3 is enabled, and the delay measurement circuits 51, 52, and 53 are enabled. At this time, the 3-state buffer 34. S5. S6 is masked and logic circuit 6 is disabled. And input terminal 2
The delay characteristics of this LSI are measured by inputting a signal of a predetermined turn to the output terminal 31, 32 or the bidirectional terminal 40c and comparing it with the signal appearing at the output terminal 31, 32 or the bidirectional terminal 40c.

Also, instead of the complicated logic circuit 7, the delay measurement circuits 51 to 5
By passing a predetermined pattern of signals through 3, the input terminal 2
1 to 23, bidirectional terminal 40, output J terminals 31 and 32,
Input buffers I2 to I4, output buffers 61 and 62
Therefore, it is possible to easily check whether or not the external interfaces, external interfaces, etc. are malfunctioning.

In other words, in the present invention, a delay measurement circuit for measuring delay characteristics is provided in addition to the original logic circuit, and when testing is performed, switching to the delay measurement circuit side is performed to verify the validity of the delay characteristics and human output buffer, etc. The test will be conducted.

As explained above, the present invention provides a delay measurement circuit for measuring delay characteristics in addition to the original logic circuit, and when testing, by switching to the delay measurement circuit side, the delay is measured. This has the effect that it is possible to easily test the validity of characteristics, human output buffers, etc.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing the configuration of an LSI according to an embodiment of the present invention. Explanation of symbols of main parts 10... Test terminals 51, 52, 53... Delay measurement circuit N...
...Inverters 31, 32. 33

Claims (1)

[Claims] (1) a logic circuit, a delay measurement circuit for measuring the delay time due to the logic circuit, an input/output buffer section of the logic circuit, and a link between the logic circuit and the delay measurement circuit to the input/output buffer section; and switching means for selectively and electrically switching and connecting the LSI.