JPS61187675A - Semiconductor apparatus - Google Patents

Abstract

PURPOSE:To attain the enhancement of reliability and the shortening of a LSI development period, by providing a testing pad at the time of die-sorter on a LSI chip. CONSTITUTION:For example, when a die-sorter exclusive pad 31 is connected to the output terminal of latch 11 and a pad 32 to the data input terminal of the latch 11 and a pad 33 to the clock terminal of the latch 11, the input data D, latch clock phi2 and output data OUT of the latch 11 can be observed by the pads 31-33. By forcibly applying signal from the pads 32, 33, data and data latch timing can be imparted freely. Therefore, by connecting the pad to each part to be measured in LSI directly or by contriving a circuit, an inter nal signal can be directly tested and, because the access from the outside of a package can not parformed even if the internal signal is directly connected to the pad as mentioned above, electrical reinforcement like the pad for a user is unnecessary. Because direct testing is enabled, a test is simple and the specification of an inferior place becomes easy and the shortening of a LSI development time can be attained.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device with an improved structure of an LSI chip.In particular, the present invention relates to a semiconductor device with an improved structure of an LSI chip. [Technical background of the invention and its problems] Conventionally, LSI die sorters have been used after the LSI has been assembled or on pads that are actually used by users who can access them from outside the device. was tested using. In testing using this conventional method, there are many internal data retention systems such as renostas that cannot be accessed directly even when using Daiso, so testing for this system was performed indirectly. For example, to test a certain part,
It executes several instructions and makes decisions based on the final results (data or pad status).

The disadvantages of this method are: 0) Since the test result is an accumulation of multiple paths, it is very difficult to estimate the actual location of the defect when it becomes defective. (b) Testing methods become complicated because direct access is not possible. The pads that are accessible from outside the E are electrically reinforced (e.g., with a Sarno protection circuit) to withstand the user's environment, making it difficult to observe the pure electrical characteristics inside the chip. .

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and by providing a test pad during die sorter to more easily perform the conventional test method, it is possible to improve reliability and, in some cases, to develop LSI. This is an attempt to shorten the period.

[Summary of the invention]

The present invention provides a pad for a guisota on the chip that cannot be accessed externally after LSI assembly, and provides an internal renostar (resota that cannot be accessed directly from the outside) necessary for the guisota, a data retention system, etc. It has a structure that allows access to Dulct. Furthermore, by performing the die sorter using a test pad and a conventional mother pad that can be used by the user, a highly reliable test can be performed.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the diagram, 1 is LSI! , 2 are connected to external lead-out pins and allow the user to access the chip circuit from outside the device after assembly of the LSI.
3 is a pad exclusively for die sorter. This motherboard 3 dedicated to the data processor cannot be accessed after the LSI is assembled.

FIG. 2 is an LSIS Noroku circuit showing a specific example of FIG. 31-3 in the figure. Reference numeral 11 indicates a pad dedicated to a guisorter, and 11 indicates a latch circuit for holding data inside the LSI, which corresponds to a resistor, an accumulator, or the like. 12 is an I-1 state buffer. The above-mentioned Guisota dedicated pad 31 is connected to the output end of the latch 1, for example, and the Guisota dedicated pad 3. For example, connect to the rotor input terminal of ratte 11,
Daisota exclusive/Mother Tsudo 3. is connected to the clock input terminal of the latch 11, for example.

If the configuration is as shown in FIG. 2, the die sorter dedicated slots 31-3. Therefore, the input data D of latch 11
1 Latch clock φ1, output data 0UTt
-You can watch it. Also pad 3. ．． 3. Data and data latte timing can also be freely given by forcibly giving a signal from .

FIG. 2 shows an embodiment of the present invention, and it is not necessarily necessary to have the same structure as this. For example, if there is a limit to the number of motherboards on the LSI chino f1, for example, a serial out resouter for a guisota may be used. The number of installed pads may be reduced by providing a serial output signal in the LSI terminal and supplying and receiving signals exclusively for the data sorter from this serial out register.

FIG. 3 shows an example of its application. In the figure Jll~3,3
is a pad exclusively for Guisota, 21.22 is a latch, 23
．． 24 is a tiger 1 state buffer. By adopting the configuration shown in FIG. 3, it is possible to observe many places with a small number of bats. That is, the observed signal inside the LSI is connected to the terminals 25 and 26, and the ratte signal (
By applying a clock signal) to the two observation terminals, the day and evening data are latched. And tiger 1 from mother Tsudo Jll
Give a 1 nable signal to the state buffers 23 and 24,
Noya Rad 31. When a clock is applied, the signal to be observed can be observed serially from pad 3□ in synchronization with the rising edge of this clock.

〔Effect of the invention〕

Conventional data sorters use only the motherboard that the user can use to test each signal and held data inside the chip. I couldn't stand Daisota. This conventional method requires a sequence for outputting the results to the outside, which is a very difficult task when testing a CPU (Central Processing Unit) or the like. According to the present invention, internal signals can be directly tested by connecting each part to be measured inside an LSI to a guisoter pad either directly or by devising a circuit.

Is the internal signal directly like this? When connected to the 14' pad, this pad is not accessed from outside the 4' pad and therefore does not require any electrical reinforcement like the 14' pad for the user. In addition, since it can be tested directly, it is easy to test, and when a failure occurs, it is easy to identify the location of the failure, and the LSI
It is also expected that development time will be shortened.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of an embodiment of the present invention, FIG. 2 is a specific circuit diagram of the same configuration, and FIG. 3 is a circuit diagram showing an application example of the same circuit.ノ...LSI step, 2...Pad usable by the user, 3,3I~31*Jjl~3□...Pad exclusively for Daisork. Applicant's agent Patent attorney Takehiko Suzue 20

Claims (1)

[Claims] A semiconductor device characterized in that a test pad for die sorting is provided on the LSI chip, in addition to a pad that allows access to the circuit of the chip from outside the package after assembly of the LSI chip.