JP2007067180A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit wherein its test time is shortened, and its testing accuracy and reliability are improved, and further, its hardware and software are simplified, and moreover, the security protection of its circuit is made possible. <P>SOLUTION: Beside a main-body chip having a constituted main-body circuit, a test circuit is integrated as a chip in the semiconductor integrated circuit. The test chip has a test terminal for inputting a test signal and outputting a test result, has a test-state setting means for resetting the main-body circuit and for so responding to the logical level of the test signal inputted at that time as to initialize a test-circuit controlling unit and as to set peripheral units to testing states, and further, has an input/output means for so performing a test according to a test command inputted via the foregoing test terminal and as to output from the foregoing test terminal the resultant data obtained by the test. The main-body chip and the test chip are disposed in respective chips which are independent of each other and are approximate to each other, and these respective chips are connected with each other on a scribe by such metal wiring as aluminum wiring. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit having a test circuit. In particular, the present invention relates to a semiconductor integrated circuit in which a test circuit added to a main circuit is considered not to adversely affect the main circuit.

  Conventionally, semiconductor integrated circuits with a small circuit scale have many simple functions and few test items. Therefore, the logic functions and electrical characteristics of a semiconductor integrated circuit can be controlled from an external terminal to an LSI tester, etc. It was relatively easy to measure with, and no special device was required. However, in recent semiconductor integrated circuits, high integration of circuit functions and diversification of electrical characteristics have progressed, and the circuit functions are often complicated and closely related to each other. In addition, circuit functions and electrical characteristics that cannot be directly tested from an external terminal by an LSI tester or the like are increasing.

  Many logic functions and electrical characteristics of circuits that cannot be tested from external terminals by LSI testers, etc. can be indirectly tested by using devices such as LSI tester test programs and measurement assisting circuits. In addition to increasing the time required for testing, if the accuracy of testing of each circuit function and electrical characteristics is maintained at the same level as the testing level of a conventional semiconductor integrated circuit having a relatively simple circuit function, It takes a very long time to develop a test program and a circuit for assisting measurement. Furthermore, because it is difficult to manage and store the circuits that support these measurements, it is almost impossible to conduct a comprehensive test for every product.

Therefore, in a semiconductor integrated circuit whose function is highly integrated, a test circuit is generally mounted in the semiconductor integrated circuit in order to perform a test with high accuracy of circuit function and electrical characteristics. . However, when a semiconductor integrated circuit as a product is used in a device requiring high reliability such as an automobile or an aircraft, the reliability of the semiconductor product is directly related to the reliability of the device. Of course, high reliability is also required for semiconductor products. In such a case, if the test circuit is combined with the semiconductor integrated circuit, it is necessary to secure the reliability of the test circuit part that is not used by the user and to eliminate the influence that the test circuit may have on the main circuit. Therefore, reliability tests such as electrostatic withstand voltage testing of test circuits and operation confirmation in high temperature environments have to be performed, which has been a drag on the development and commercialization of semiconductor circuits themselves. (For example, see Patent Document 1)
JP 2001-267510 A

  In the semiconductor integrated circuit having the conventional test circuit described above, the test circuit is arranged on the same chip, and a test terminal and a test mode for moving the test circuit are necessary. Therefore, not only a special design method or a reliability test for increasing the reliability of the test circuit is required, but also the design of the main circuit is restricted due to the presence of the test circuit.

  Furthermore, there is a problem that many techniques and know-how are required for the external hardware and software used for the test in order to maintain the design confidentiality of the internal circuit and the semiconductor integrated circuit.

  An object of the present invention is to reduce the test time, improve the test accuracy and reliability by removing the above-mentioned problems, simplify the hardware and software, and keep the circuit confidential. There is to be able to do it.

  In the present invention, when a reset signal is input to an external reset terminal, one test terminal for inputting a test signal and outputting a test result, on the semiconductor integrated circuit, separately from the main body chip in which the main body circuit is configured And a test state setting means for resetting the main body circuit and initializing the test circuit control unit in response to the logic level of the test signal input at that time to set the peripheral unit to the test state, After the peripheral unit is ready for testing by the test state setting means, a test is performed by setting test conditions for the peripheral unit based on data obtained by serial-parallel conversion of a test command input via the test terminal, The test result data thus obtained is converted from parallel to serial data and output from the test terminal. And a output means for, in which integrated on one chip test circuitry as test chip. The main body chip and the test chip are arranged in separate chips, and these chips are connected by a metal wiring such as aluminum on the scribe.

  As described above, according to the present invention, since the test circuit of the semiconductor integrated circuit is located in an adjacent chip and is separated and discarded after the test is completed, the confidentiality of the test contents can be kept high. The test time for ensuring the reliability of the main circuit can be greatly shortened while ensuring the reliability of the circuit.

Best Mode for Carrying Out the Invention

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. A semiconductor integrated circuit composed of a main circuit and a test circuit stores a main circuit 11 having an external reset terminal 1, an external interrupt terminal 10, a reset terminal 2 and an interrupt terminal 12, and an initialization program when a test circuit activation request is made. The present invention includes, for example, an ion implantation mask ROM (read only memory) 9, a peripheral unit 13, a test circuit control unit 17 for each unit, an in-chip signal bus 16, and a peripheral bus 21. A test terminal 8 for inputting a test signal and outputting a test result, an external reset signal input to the external reset terminal 1 and a test signal input to the test terminal 8 are detected to test the semiconductor integrated circuit. Reset signal edge detection circuit 3 as test state setting means for setting the state, test end The level detection circuit 6, the test flag circuit 7, the OR circuit 20, the serial / parallel conversion circuit 14, and the input buffer 15, an output buffer 18 as output means for outputting a test result from the test terminal 8, and a parallel / serial conversion circuit 19 are included. It is out.

  Further, the main circuit is configured in a separate chip so as to be a chip A (main body chip) and the test circuit is a chip B (test chip). Chip A and chip B are connected by wiring made of aluminum or the like on the scribe.

  Next, the operation of this embodiment will be described.

  The external reset signal input from the external reset terminal 1 is supplied to the reset signal edge detection circuit 3 while being supplied to the reset terminal 2 of the main circuit 11 as a normal reset signal in the semiconductor integrated circuit. The reset signal edge detection circuit 3 falls and detects the change point of the reset signal (pulse), and detects the falling edge detection result signal 4 and the rising edge detection result signal 5 to the test terminal level detection circuit 6. give.

  When the falling edge detection result signal 4 is input, the test terminal level detection circuit 6 clears the test flag circuit 7 and scans the input level of the test terminal 8, and the input level of the test terminal 8 becomes “test circuit activation requested”. If the input level is set, the test flag circuit 7 is set when the rising edge detection result signal 5 is input.

  The contents of the test flag circuit 7 are supplied to the bus connection circuit of the ROM 9, the ROM 9 is arranged on the memory address space only when a test circuit activation request is made, and an interrupt signal and an OR circuit input to the external interrupt terminal 10 of the semiconductor integrated circuit A logical sum is obtained at 20 and supplied to the interrupt terminal 12 of the main circuit 11 as an interrupt signal IINT.

  The body circuit 11 starts initialization of the body circuit 11 itself at the falling edge of the reset signal, and finishes initialization of the body circuit 11 itself in a time shorter than the reset pulse period specified in the catalog specification. When the main circuit 11 receives the interrupt signal IINT at the interrupt terminal 12 immediately after resetting the main circuit 11 itself, the main circuit 11 immediately enters the interrupt process for controlling the test circuit, and the initialization program at the time of the test circuit activation request is stored. In accordance with the ROM 9, the peripheral unit 13 itself performs initial setting, control signal switching, and the like, and the test circuit control unit 17 on the chip is activated to prepare the peripheral unit 13 for testing.

  When the test preparation is completed, the test terminal 8 becomes a serial input terminal for giving a test command to the main circuit 11. The 4-bit serial signal input from the test terminal 8 is converted into a parallel signal by the serial-parallel conversion circuit 14, and then the 16-bit in-chip signals are arranged in the bus image by the input buffer 15, and each 16-bit chip. Take the internal signal bus 16.

  The main circuit 11 transfers this test command to the test circuit control unit 17 for each unit provided for each peripheral unit to be tested, or transfers necessary data. The test circuit control unit 17 sets the test conditions of the peripheral unit 13 according to the test command and data, and switches the connection of the output buffer 18 that accumulates the test result once according to the path through which the peripheral unit 13 outputs the test result.

  When the last data for setting the test condition is transferred to the test circuit control unit 17, the test terminal 8 becomes a serial output terminal for outputting the test result of the peripheral unit 13 to the outside of the semiconductor integrated circuit.

  The test results of the peripheral unit 13 are accumulated once in the output buffer 18 and then sent to the parallel-serial conversion circuit 19 every 4 bits and output from the test terminal 8 as 4-bit length serial data.

  In this embodiment, since the test circuit setting from the semiconductor integrated circuit to the test result extraction can be performed by one test terminal 8, not only the inspection by the LSI tester but also the semiconductor integrated circuit on the motherboard of a device such as a microcomputer. The semiconductor integrated circuit can be inspected with a simple serial transceiver while attached.

The block block diagram which shows the 1st Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 External reset terminal 2 Reset terminal 3 Reset signal edge detection circuit 4 Falling edge detection result signal 5 Rising edge detection result signal 6 Test terminal level detection circuit 7 Test flag circuit 8 Test terminal 9 ROM
DESCRIPTION OF SYMBOLS 10 External interrupt terminal 11 Main body circuit 12 Interrupt terminal 13 Peripheral unit 14 Serial parallel conversion circuit 15 Input buffer 16 In-chip signal bus 17 Test circuit control unit 18 Output buffer 19 Parallel serial conversion circuit 20 OR circuit 21 Peripheral bus

Claims (3)

A semiconductor integrated circuit comprising a main body chip provided with a main circuit and a test chip provided with a test circuit;
The test circuit includes:
One test terminal for inputting test signals and outputting test results,
An external reset terminal,
A test circuit control unit;
With peripheral units,
When a reset signal is input to the external reset terminal, the main body circuit is reset and the test circuit control unit is initialized in response to the logic level of the test signal input at that time to test the peripheral unit A test state setting means for setting the state;
After the peripheral unit is ready for testing by the test state setting means, a test is performed by setting test conditions for the peripheral unit based on data obtained by serial-parallel conversion of a test command input via the test terminal. Input / output means for parallel-serial conversion of the test result data obtained thereby and outputting from the test terminal;
A semiconductor integrated circuit in which the main body circuit and the test circuit are connected by metal wiring on a scribe line. The test state setting means includes
A reset signal edge detection circuit for detecting a change point of an external reset signal input to the external reset terminal;
A test terminal level detection circuit that receives a signal from the reset signal edge detection circuit and monitors an input level of the test terminal;
A test flag circuit set by the test terminal level detection circuit;
2. The semiconductor integrated circuit according to claim 1, further comprising an OR circuit that takes a logical sum of an output from the test flag circuit and an input signal from an external interrupt terminal and outputs a signal to the interrupt terminal of the main circuit. The input / output means includes
A serial-parallel conversion circuit connected to the test terminal;
An input buffer for supplying the output of the serial-parallel conversion circuit to an in-chip signal bus;
An output buffer for receiving data from the on-chip signal bus;
A semiconductor integrated circuit comprising a parallel-serial conversion circuit for supplying a signal from the output buffer to the test terminal.

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