JPS5852580A - Device for testing integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a measured data regarding a switching characteristic of an IC to be measured, by testing plural unit functions is order at every 1 unit function, and storing the maximum value or the minimum value among measured values obtained from the test. CONSTITUTION:A titled device is provided with a time measuring circuit 1 which is initialized by the first timing signal 5 from a timing generator 3, starts a time measurement by the second timing signal, and ends each time measurement by a signal as a result of comparing an output of an IC2 to be measured, with a comparison reference value 8, and a maximum value holding circuit 11 for holding the maximum value among the measured values by the circuit 1. A characteristic data of one cell is held in the circuit 11 which is initialized when starting a test of a data collecting object test item in 1 cycle. Subsequently, the same test is executed as to other one cell, data obtained extending over the whole read cycle are held in the circuit 11, and when the test of the data collecting object test item has ended, a characteristic data can be obtained from this value.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit testing apparatus, and more particularly to an apparatus for obtaining measurement data relating to switching characteristics of an integrated circuit under test among characteristic data.

The most effective information for performing process control in each manufacturing process of integrated circuits (hereinafter referred to as IC) is characteristic data obtained from product measurement. Collection of this characteristic data is performed using a data collection function attached to an integrated circuit testing device (hereinafter referred to as an IC tester).

This data collection function is used to obtain characteristic data distribution information for one or more data collection target test items for all or a specific part of the IC under test in an operation test that has multiple test items. It is a function.

Examples of data collection means for this data collection function include the following.

For the test item for which data is to be collected in the operation test, the test parameters that make it possible to quantitatively obtain characteristic data are first set to initial values, the test item is tested, and the logical result of the test item is determined. get. Next, the test parameters are changed by the predetermined values, and the test item is tested in the same manner as the previous time to obtain two logical results of the test. The above is a logical result of n (n: integer) and n+
The test is repeated until the logical result of 1 is logically different, and characteristic data is obtained quantitatively from the test parameters in the n-th test.

That is, assume that a test is performed under certain conditions, and the test result is output as defective. Next, the test is conducted again under certain conditions that are slightly different. This test is repeated many times until the result is satisfactory. This is to determine the test conditions under which the test result changed from poor to good.

However, according to the above method, in order to collect the necessary characteristic data as a measurement, it is necessary to conduct the test multiple times, and the characteristics of the IC to be measured may be affected due to the heat generation of the IC to be measured due to repeated testing. Also, since the data collection is performed during the production process, the time required to measure the product becomes longer.

This results in an increase in the cost of the product.

An object of the present invention is to provide an integrated circuit testing apparatus having a measuring means free from such problems.

The present invention provides a means for sequentially testing a plurality of unit functions of a semiconductor element having a plurality of unit functions, one unit function at a time, and a means for sequentially testing the plurality of unit functions of a semiconductor element having a plurality of unit functions, and a means for sequentially testing the plurality of unit functions of a semiconductor element having a plurality of unit functions. and means for storing the information.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a waveform diagram of each signal in FIG. 1. To explain a memory IC as an IC to be measured, in one read cycle in a certain measurement test drive, one or more cells (aligned memory elements) in a semiconductor element are selected by an address signal from a tester. The operation of outputting the information in the cell to the output terminal is sequentially performed for all cells. However, the time υ from when the individual cells are selected to when the output is output is different, and the maximum time υ becomes the metric characteristic data of the iC to be measured. In other words, this characteristic data is used as the standard for the IC based on the cell with the slowest operating speed.

In the configuration shown in FIG. 1, initial values are initialized by a first timing signal 5 from a timing generator 3, time measurement is started by a second timing signal 6, and the output of the integrated circuit under test 2 is used as a comparison standard. [8] A time measurement circuit 1 which terminates each time measurement by a signal resulting from the comparison with 8; and a maximum value holder which holds the maximum value among the plurality of measured values by the time measurement circuit 1.

It consists of a holding circuit 11, etc.

In the operation test of this embodiment, the operation in the first one read cycle is as follows, as shown in FIG.

The time measurement circuit 1 is initialized by a first timing signal (hereinafter referred to as the STC signal) 5 that serves as a reference for the measurement signal 4 from the timing generator 3 applied to the IC under test 2.
Time measurement is started using a second timing signal, that is, a TST signal 6, which can be delayed by an arbitrary amount of time from the STC signal 5. Furthermore, the output of the IC under test 2 is connected to one input of a comparator circuit 9 that can arbitrarily set an IJ value of 8, and when a certain period of time has elapsed since the STC signal 5, the output of the IC under test 2 is When the cuff exceeds the limit value 8, the output 12 of the comparator circuit 9 changes logically, causing the time measuring circuit 1 to stop measuring time and output a measured value 10. This measured value is then stored in the maximum value holding circuit 11. thus,
Characteristic data of one cell can be obtained. The measurement [10] obtained in the above manner within one cycle is connected to the maximum value holding circuit 11 which is initialized at the start of the test of the test item to be data collected. A similar test is then performed on another cell. The maximum value among the plurality of measured values obtained in the above manner over all read cycles is held in the holding circuit 11. Characteristic data can be obtained from this saliva at the end of the test for the data collection target test item.

As described above, according to the present invention, it is possible to obtain metrological characteristic data through a single fc test. It becomes possible to obtain characteristic data of the measurement IC.

In addition, as an embodiment of the present invention, the cell of the memo IJIC is =
6- However, the unit function of the present invention is not limited to this, and includes various unit logic elements and combination units thereof.

Further, although the configuration of the embodiment of the present invention is such that the maximum measured value is stored, the present invention is not limited to this, and conversely, the minimum measured value is stored with respect to noise margin, etc. Since there is a need to do so, in this case a means for storing the smallest thing is included.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a waveform diagram of the embodiment of the present invention. 1 in the plan
Time measurement circuit, 2... IC to be measured, 3...
...Timing generator, 4...Measurement signal, 5.
...STC signal serving as a reference for the measurement signal, 6...
...TNT signal that can be delayed arbitrarily from the STC signal,
7... Output of IC under test, 8... Limit case, 9... Comparator circuit, 10...
. . . Output of the time measurement circuit, 11 . . . Maximum value holding circuit, 12 . . . Output of the comparator circuit.

Claims (2)

[Claims] (1) In an integrated circuit testing device for testing a semiconductor device having a plurality of unit functions, there is provided a means for sequentially testing the plurality of unit functions one by one, and a means for sequentially testing the plurality of unit functions one by one; an integrated circuit test device comprising: means for storing a memory or a smallest memory; (2) The integrated circuit testing apparatus according to claim (1), wherein the unit function to be tested is a cell of a memory element.