JPH01233377A - Function test - Google Patents

Abstract

PURPOSE:To reduce a test time with a greater test speed, by generating a test input pattern using an exclusive OR between a fixed value data output per specified cycle and a timing pulse having the same cycle as that of the data output and a width narrower than the data output. CONSTITUTION:In the generation of an input pattern, a test input pattern is generated using an exclusive OR between a data output taking a value binary and determined at each specified cycle and a timing pulse having the same cycle as, and a width narrower than, the data output. As the data output and the timing pulse are both binary and the width of the timing pulse is narrower than that of the data output, there is sure to be a part having the data output level coinciding with the timing pulse level and that having none within one cycle. Thus, two different DC levels can be generated within one cycle by obtaining an exclusive OR between the these parts, thereby enabling a reduction in the test time.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a function test method that checks whether the expected output is obtained by inputting a predetermined combination of DC levels to predetermined terminals of an LSI, etc., by increasing the test speed. For the purpose of shortening the test time, the data output that takes two predetermined values at each predetermined period is excluded from the timing pulse that has the same period as the data output and is narrower than the data output. The test input pattern is configured to be generated using logical disjunction.

[Industrial application field]

The present invention relates to a function test method for inputting a predetermined combination of DC levels to predetermined terminals of an LSI or the like and checking whether an expected output is obtained.

For function tests to check whether circuits on LSIs etc. function normally, a combination of predetermined DC levels is input to a predetermined terminal of the circuit under test such as an LSI, and the expected DC level is measured. There are those that test whether or not the output is output, and those that test the timing.

The present invention relates to the former.

Conventionally, in LSI function testing, LSI
The input pattern to be input to each predetermined terminal of Using a timing generator that outputs narrow timing pulses,
It was created by generating one DC level for each period of the output of these pattern generators and timing generators.

Incidentally, the upper limit of the speed of conventional function tests is determined by the frequency of the outputs of the pattern generator and timing generator. However, for functional testing of LSIs and the like, it is necessary to sequentially test a very large number of combinations of DC levels, and there has been a need for a technology that can speed up the testing and shorten the testing time.

[Prior art and problems to be solved by the invention]

FIG. 4 shows a configuration example of a conventional input pattern generation circuit for functional testing.

In FIG. 4, 1 is a pattern generator, 2 is a timing generator, 4 is a flip-flop circuit, and 5 is an AND circuit.

The pattern generator outputs data of a predetermined value at each predetermined period. The timing generator outputs a timing pulse having the same period as the data output of the pattern generator and narrower in width than the data output.

The above-mentioned timing pulse is applied to the edge trigger input terminal of the flip-flop circuit 4, and the data output of the above-mentioned pattern generator 1 is applied to the data input terminal.

On the other hand, the timing pulse and the data output of the pattern generator 1 are also applied to two input terminals of the AND circuit 5.

The timing for the configuration of FIG. 4 is shown in FIG. In FIG. 5, CLK indicates the output of timing generator 2 of FIG. 4, DATA indicates the data output of pattern generator 1 of FIG. 4, and NRZ indicates the output of timing generator 2 of FIG. 4. The output of the flip-flop circuit 4 and indicated by RZ in FIG.
This is the output of the AND circuit 5 in FIG.

As shown in FIG. 5, the output NRZ of the flip-flop circuit 4 changes at each rising timing of the timing pulse output from the timing generator 2, depending on the level of the data input DATA at that time.

Also, the output of the AND circuit 5 is that the data input DATA is 1.
In the cycle of the H level, it is equal to the timing pulse, and in the cycle of the data input DATA at the L° level, it remains at the "L" level.

As described above, the conventional input pattern for the function test is such that one DC level is output for each cycle of the pattern generator and timing generator.

However, according to the above-described conventional test input pattern generation method for a function test, the speed of the function test is limited by the frequency of the outputs of the pattern generator and timing generator. However, in order to test the function of an LSI, it is necessary to sequentially test a very large number of combinations of DC levels, and the conventional method has a problem in that the test takes a long time.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a function test method that increases the test speed and shortens the test time.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention. As shown in this figure, in the function test method of the present invention, the input pattern is generated using a data output that is binary and takes a predetermined value at each predetermined period, and a data output that is the same as the data output. A test input pattern is generated using exclusive OR with a timing pulse having a period and a width narrower than the data output.

[For production]

Both the data output and the timing pulse are binary, and the width of the timing pulse is narrower than the width of the data output.
Within one cycle, there are always parts where the level of the data output and the level of the timing pulse match and parts where they differ. Therefore, by taking the exclusive OR of these, two different DC levels can be generated within one cycle.

Therefore, the test time can be reduced compared to the conventional method.

〔Example〕

FIG. 2 shows a configuration for generating an input pattern in an embodiment of the present invention. In FIG. 2, the pattern generator 1 and timing generator 2 are
This is similar to that shown in FIG. 4 above. In the configuration of FIG. 2, the data output DATA output from the pattern generator 1 and the timing pulse CLK output from the timing generator 2 are each EX-N
It is applied to two input terminals of the OR circuit 3. - FIG. 3 shows a timing diagram of input pattern generation according to the configuration of FIG. 2.

As shown in FIG. 3, the width of the timing pulse is narrower than the width of the data output, so within one cycle there are parts where the level of the data output and the level of the timing pulse match and parts where they differ. do. Therefore, EX
In the output EX-NOR of the -NOR circuit 3, two different DC levels exist within one cycle. For example, the third
If measurements are taken at the timings shown at t+, b, h, and ta in the lower part of the figure, two DC
A functional test can be performed for the level. In this way, according to the function test method of the present invention, the test time can be shortened compared to the conventional method in which a function test is performed for only one DC level in one cycle.

〔Effect of the invention〕

According to the function test method of the present invention, the test speed can be increased and the test time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the principle of the present invention; FIG. 2 is a diagram showing a configuration for generating an input pattern in an embodiment of the present invention; FIG. 3 is a timing diagram for generating an input pattern according to the configuration of FIG. 2; FIG. 4 is a diagram showing an example of the configuration of an input pattern generation circuit for a conventional function test, and FIG.
FIG. 3 is a timing diagram of a conventional input pattern according to the configuration shown in the figure. [Explanation of symbols] 1... Pattern generator, 2... Timing generator, 3... EX-NOR circuit, 4... Flip-flop circuit, 5... AND circuit. Figure 4 t1' is a diagram showing an example of the configuration of an input pattern generation circuit. Figure 5 is a timing diagram of a conventional input pattern with the configuration shown in Figure 4.

Claims (1)

[Claims] Using the exclusive OR of a data output that is 1 or 2 and takes a value determined every predetermined period, and a timing pulse that has the same period as the data output and is narrower in width than the data output. A function test method characterized by generating a test input pattern using