JPH02206771A - Device and method for forming pattern - Google Patents

Abstract

PURPOSE:To easily form an optional pattern without limiting hardware by reading out transition time information and logical value transition information stored corresponding to the transition time information and setting the logical change of an event as a pattern following the flow of time. CONSTITUTION:The logical value transition information and the transition time information which are paired and stored in the memory 20 of an inspection pattern forming part 14 are read out. When the transition time information coincides with the counted value by a clock counter 25 which counts a clock, a latch circuit 24 is controlled with coincidence output from the comparator 22 so as to output the latched transition time information in synchronism with the clock and the logical value transition information read out from the memory 20 is latched. At the same time, an address counter 21 is counted up with the coincidence output and the logical change of the event is outputted as the pattern following the flow of time by repeating the above-mentioned operation.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a signal pattern generation technique, and is applicable to, for example, the formation of input test sequences and output expected value sequences used for logic verification of semiconductor integrated circuits. It is about effective techniques.

[Prior art]

Logic verification of various semiconductor integrated circuits such as logic LSIs is performed by applying a series of input test sequences to the LSI under test and comparing the validity of the output response sequence with an output expected value sequence. The LSI under test includes not only combinational circuits such as simple gates, but also sequential circuits, and the logic depth thereof is considerably deep. Therefore, test patterns such as input test sequences and output expected value sequences are based on truth tables and pool formulas. Mere logical value information as expressed by is not enough; timing must also be taken into account. Conventionally, a test pattern used for logic verification of semiconductor integrated circuits consists of a logic pattern output from a pattern generator and a required clock signal generated by a timing generator, with a period based on a reference timing output from a timing generator. By logically synthesizing the
It is generated by selecting a waveform mode with a predetermined timing such as Z (non-return to zero). In this way, conventionally, a logic value is extracted according to a set predetermined cycle, and a waveform of the corresponding cycle is determined according to a predetermined waveform mode according to the extracted logic value.

Incidentally, examples of documents describing test pattern formation techniques in semiconductor integrated circuit test equipment include 19
There is rsEMIcON NEWSJ P54-P62 published by Marcom International Co., Ltd. in March 1986.

[Problem to be solved by the invention]

However, with the conventional technology of extracting logical values according to a predetermined period and determining the waveform of the corresponding period according to the extracted logical value according to a predetermined waveform mode, the test patterns that can be formed are limited by the hardware. There was a problem that That is, the types of waveforms and change timings of test patterns that can be formed are limited by the minimum to maximum range of settable cycles and the types of waveform modes that can be set.

Given these limitations, in situations where the number of external pins increases as semiconductor integrated circuits become more highly integrated and logic becomes more complex, it becomes difficult to simultaneously supply test patterns with different timing or waveforms to many external pins. This makes it difficult to verify the logic.

Furthermore, as the logic design of semiconductor integrated circuits becomes more highly integrated and logic becomes more complex, automation of logic design is progressing, and the results of LSI logic simulation obtained in this process can be compared to the actual LSI.
It is considered desirable to link SI logic verification, that is, to unify automatic device design and device testing, in order to shorten the TAT (turn around time) of semiconductor integrated circuits. , - Since logic simulation results in the membrane take a format that expresses changes in logical events according to the flow of time, as in the past, logic values are extracted according to a predetermined cycle, and the waveform of the corresponding cycle is generated according to the extracted logic value. If a test pattern is formed using a technique in which the waveform is determined according to a predetermined waveform mode, it is not possible to easily link the logic simulation results to the LSI test.

It is an object of the present invention to provide a pattern generation device and a pattern generation method that can easily form arbitrary patterns without being limited by hardware. It is an object of the present invention to provide a pattern generation device and a pattern generation method that allow the results of a test to be easily used in an LSI test.

The above and other objects and novel features of the present invention are as follows:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a series of logical value transition information indicating a transition state of a logical value is associated with transition time information indicating a change timing of a logical value in the logical value transition information, and the logical value transition information is calculated based on the transition time information. Adopts a method of forming logical changes in events into a pattern that follows the flow of time while sequentially reading data from the storage means according to a defined time,
Furthermore, this method is applied to a pattern generator.

When forming an input test sequence or an output expected value sequence for a semiconductor integrated circuit using such a method, a pattern generation unit using the method can be configured for each signal or pattern.

[For production]

According to the above-mentioned means, a change in a logical event is formed as a pattern having a predetermined logical value and timing according to the flow of time corresponding to the transition time information. This works to easily form any pattern without being limited by hardware by programmably changing the logical value transition information and transition time information.

A pattern formation method that associates a series of logical value transition information indicating the transition state of a logical value with transition time information indicating the timing of change of the logical value in the logical value transition information is a method that can detect changes in logical events. Basically consistent with the format of logical simulation results expressed according to the flow of time, L
This makes it possible to easily link SI logic simulation results to actual LSI tests.

In addition, configuring the pattern generation section as a unit so as to form an input test series and an output expected value series for each external terminal of the semiconductor integrated circuit to be tested means that only the necessary signal patterns can be used to generate other signals. It works so that it can be easily changed without affecting the pattern.

〔Example〕

FIG. 9 shows a block diagram of a logic verification LSI for the LSI to be tested. Logic verification LSI shown in the figure
I is applied to an LSI test system, for example, a random logic L such as a microprocessor.
By applying a series of test patterns to the LSI under test 2 such as an SI through the output port 3, and taking in the output response from the input port 4 and comparing its validity with the expected output value pattern, the LSI under test 2 can be tested. It supports logical verification. System control for this logic verification LSI 1 is performed by a host system 6 connected via a host interface 5. This host system 6 is centered around a host processor, and has peripheral devices such as a keyboard, a display, a printer, a magnetic disk device, and a floppy disk device.
Configure systems, engineering workstations, etc.

The logic verification LSII is formed on a single semiconductor substrate such as silicon by a known semiconductor integrated circuit manufacturing technique. This logic verification LSII has an internal bus 10 connected to the host interface 5, and a processor 11 that controls the overall control of the LSII,
A memory 12 used as a work area and a data buffer of the processor 11, a direct memory access controller 13, a test pattern generator 14 that supplies a series of test patterns to the LSI under test 2 via an output port 3, and Tested LS for test pattern
An expected value pattern generating section 15 that forms an output expected value pattern to be compared with the output response of I2 is coupled thereto. The output response of the LSI under test 2 receiving the input test pattern is given to the comparison/judgment section 16 via the input port 4, and is compared with the output expected value pattern by the comparison/judgment section 16. The comparison timing by this comparison/judgment section 16 is as follows:
The comparison timing generator 17 provides the comparison timing in consideration of the time from supplying the input test pattern to obtaining the output response. The pass/fail determination result and defect location in the comparison determination unit 16 are stored in the fail analysis memory unit 18, and the stored contents are later provided to the host system 6 under the control of the processor 11 and direct memory access controller 13. It will be done. In addition, LSII for logic verification
Not only the internal operations of the LSX 2 but also the operations of the LSX 2 to be tested are synchronized with each other by a predetermined clock signal.

FIG. 1 shows an example of the test pattern generating section 14. As shown in FIG. The test pattern generation section 14 shown in the figure includes n units 14 in one-to-one correspondence with the output terminals of the output port 3.
Consisting of U1~14Un, each unit 14U,...~14
Un can independently form a signal pattern to be output. Each of the units 14U to 14Un has the same configuration, and the unit 14U1 whose details are representatively shown has a memory 20 such as a high-speed accessible SRAM (static random access memory). have In this memory 20.

A series of logical value transition information indicating the transition state of the logical value of the test pattern to be applied to a predetermined input terminal of the LSI under test 2 and transition time information indicating the timing of change of the logical value in the logical value transition information are paired. They are stored in an accessible manner in order starting from a predetermined starting address.

Here, an example of logical value transition information and transition time information will be explained. For example, the logical value transition information and transition time information corresponding to the waveform i on the virtual time axis shown in FIG. 2 are as shown in FIG. 3 (A) when time To is the origin of the time axis t. A pair of the time T4 at which the logical value "0" of the waveform starting from the origin TO is changed and the logical value "0" up to that time T4, as shown in FIG.
The logic value "1" of the waveform starting from time T4 is sequentially expressed by a pair of time T6 at which the logic value "1" is changed and the logic value "1" up to that time T6, and in this expression, the time T4 is digitally encoded.゜T6. ... is taken as transition time information Ti, and the logical value rQJ "1", . . . is taken as logical value transition information Li. Furthermore, the logical value transition information and transition time information corresponding to the waveform j on the virtual time axis shown in FIG. 2 are as shown in FIG. 3 (B) when TO is the origin of the time axis t. The logical value r of the waveform starting from the origin TO
Pair of the time T1 at which OJ is changed and the logical value “0” up to that time TI. The logical value “1” of the waveform starting from time T1.
The logical value "1" between the time T5 when the value is changed and the time T5 is changed.
”, the logical value [0] of the waveform starting from time T5 is changed to time T7, and the logical value “0” up to that time T7.
", and digitally coded times Tl, T5 in this representation
．． T7゜... is the transition time information Tj, and the logical value rOJ
.

r, tJ, rOJ,... are logical value transition information L
It is assumed that j. Similarly, the logical value transition information and transition time information corresponding to the waveform k on the virtual time axis shown in FIG. 2 are as shown in FIG. 3 (C) when To is the origin on the time axis. As shown in FIG. The digitally coded times T2, T5, and T5 are sequentially expressed by combinations such as pairs with logical values rlJ up to T5, and in this expression, digitally coded times T2, T5, A are taken as transition time information Tk, and logical values rOJ, rlJ, . . .
is calculated as logical value transition information Lk. Note that the origin TO in the digitally encoded transition time information corresponds to all bits O.

Such logical value transition information and transition time information can be obtained by using logic simulation results for LSI logic verification on a computer that has a format that expresses changes in logical events according to the flow of time. Can be done. For example, when focusing on the input states of specific input terminals Pi, Pj, and Pk in the logic simulation results for the LSI under test 2, the changes in these inputs are based on the virtual It is given as a change in logical value information according to time information T that expresses the flow of time. Such time information T and logical value information form a signal waveform i+ as shown in FIG.
j+k, the time information T4 when the logic value information corresponding to the input terminal Pi in FIG. 4 changes from logic "0" to logic "1" and the logic value before that change occurs.
0'', the transition time information Ti and logical value information Li are obtained by a pair of information connected by a solid line, and similarly, the pair connected by a broken line in FIG. 4 provides the transition time information Tj. and logical value information Lj are obtained, and the transition time information Tk and logical value information Lk are obtained by the pairs connected by two-dot chain lines in FIG.

The transition time information and logical value transition information, which can be easily obtained using the logic simulation results in this way, are calculated based on the logic simulation results held by the host system 6, are transferred to the memory 20, and are Each pair of information is stored in order from a predetermined start address so that the pair of logical value transition information and transition time information forming the ``transition time information'' is placed at the same address. For example, the unit 14U of the inspection pattern generator 14 has transition time information Ti.
and logical value transition information Li are stored in chronological order, and the unit 14U2 stores transition time information Tj and logical value transition information L.
j are stored in chronological order, and transition time information Tk and logical value transition information Lk are stored in chronological order in the unit 14U3.

The access address of the memory 20 is generated by an address counter 21. This address counter 21 is initialized by the processor 11, and thereafter is sequentially incremented each time the match detection signal φcomp of the comparator 22 is asserted. When the memory 20 is read accessed according to the output of the address counter 21, one of the paired transition time information Ti and logical value transition information Li
The sets are read simultaneously. The read logical value transition information is supplied to the latch circuit 24, and the read transition time information is supplied to the comparator 22.

The comparator 22 is sequentially supplied with the count value of a time counter 25 that counts the clock signal CLK, and the comparator 22 compares and determines whether the count value matches the transition time information. The time counter 25 starts a time measurement operation from an initial value in synchronization with the timing at which the address counter 21 is reset, for example. The start of this operation is instructed by the processor 11. The transition time information T i is logical information representing virtual time on the time axis using a digital code, and the correspondence between this virtual time information and physical time is determined by the time measurement speed by the time counter 25, that is, the clock. It is defined by the frequency of signal CLK. For example, when the count value of the time counter 25 is first
Transition time information given to “0~100J (T4)
when reached.

The address counter 21 is incremented, and thereby the next transition time information "0~110" and the logical value transition information "1" are simultaneously read out from the memory 20. In this way, the memory 20 is sequentially read accessed according to the physical time interval determined by the transition time information and the frequency of the clock signal CLK.

The logical value transition information read out from the memory 20 at each physical time interval may be supplied to the output port 3 as is, but in this embodiment in particular, it is supplied to the output port 3 via the latch circuit 24. This latch circuit 24 latches the logic value "0", which is the first logic value transition information, in synchronization with the timing when the address counter 21 is initialized, and thereafter the coincidence detection signal φC output from the comparator 22.
Bit data is latched in synchronization with the assertion timing of omp. Especially this latch circuit 24.

It has logic that delays the latch timing at least by the delay time from when the address signal applied to the memory 20 is changed until the output is determined, and the delay time is determined by the assertion timing of the coincidence detection signal φcomp and the address counter. The initialization timing for 21 is set as a predetermined number of cycles of the clock signal CLK. Due to this.

When the memory 20 is read accessed according to the physical time interval determined by the transition time information and the frequency of the clock signal CLK, regardless of the access delay time of the memory 20, no data is given to the outside of the unit 1-14U. The change timing of the logical value transition information is determined by the clock signal CL.
Synchronize with K.

In this way, the test pattern generation unit 14 stores in the memory 20 a series of logical value transition information indicating the transition state of the logical value and transition time information indicating the change timing of the logical value in the logical value transition information. The logical value transition information is sequentially stored in the memory 2 according to the time defined by the transition time information.
By reading from 0, logical changes in events can be formed as a pattern that follows the flow of time.

According to the present embodiment, the test patterns Di, Dj, and Dk respectively output from the units 14U□ to 14U of the test pattern generating section 14 have the waveform 1rJ shown in FIG.
yk, and the unit interval of the virtual time axis t at that time is determined by the period of the clock signal CLK.

By programmably changing the logic value transition information and transition time information stored in the memory 20 in the test pattern generating section 14, any test pattern can be easily formed without being limited by hardware. In particular, the test pattern generating section 14 of this embodiment is unitized to form a test pattern for each external terminal of the LSI to be tested, so when changing the test pattern, necessary pattern transition time information and logic Only value transition information can be easily changed without affecting other test patterns. By selecting the frequency of the clock signal CLK, the duty or pulse width of the test pattern can be arbitrarily determined.

FIG. 5 shows another example of the test pattern generating section 14. The test pattern generating section 14 shown in FIG. 5 is different in that the units 14U to 14Un shown in FIG. 1 are combined into one. In such a configuration, the transition time information Ta and logical value transition information La stored in the memory 20 are as follows:
For example, when obtaining a waveform 1y j+ k as shown in FIG. 2 using the logic simulation results in FIG. 4,
The transition time information Ta is shared with the logical value transition information La corresponding to each waveform, resulting in a configuration as shown in FIG. In this configuration, the configuration of the test pattern generation section 14 is simplified, but since the transition time information Ta is shared with the logical value transition information La corresponding to each waveform, If the transition time information or logical value transition information is to be partially changed in order to modify the waveform, the change will not be as easy as in the configuration shown in FIG.

FIG. 7 shows yet another example of the test pattern generating section 14. In the explanation of FIGS. 1 and 5, the transition time information indicating the change timing of the logical value in the logical value transition information is given as time information on a continuous time axis with the origin TO as a reference. The test pattern generation unit 14 shown in the figure has a configuration suitable for using the interval time between changing points of logical values as transition time information2. When obtaining a waveform i as shown in FIG. 2, the transition time information Tit and the logical value transition information Lit are such that the logical value "0" of the waveform i starting from the origin TO becomes the logical value "1" as shown in FIG. A pair of the interval time I4 until the logic value rOJ changes to , and the logic value rOJ at that time, and the interval time 2 and the logic at that time until the logic value "1" of the waveform starting from time T4 changes to the logic value rOJ Value "1"
The interval times I4 . I
2. ... is the transition time information Tit, and the logical value rOJ
, rlJ, . . . become logical value transition information Lit.

When such transition time information Tit and logical value transition information Lit are stored in the memory 20, the time counter 25 is reset each time the coincidence detection signal φQ Omp of the comparator 22 is asserted.

Note that the expected value pattern generating section 15 and the comparison timing generating section 17 can also be configured in the same manner as the above-mentioned test pattern generating section 14.

According to the above embodiment, the following effects can be obtained.

(1) A series of logical value transition information indicating the transition state of the logical value and transition time information indicating the timing of change of the logical value in the logical value transition information are stored in correspondence in order in the memory 20, and the memory 20 By adopting a method of sequentially reading logical value transition information by determining the access interval of the transition time according to the time defined by the transition time information read immediately before and the frequency of the clock signal CLK, the time corresponding to the transition time information can be determined. A pattern with a predetermined logical value and timing can be formed according to the flow.

(2) From the above effects, by programmably changing the logical value transition information and transition time information and storing it in the memory 20, and further by arbitrarily selecting the frequency of the clock signal CLK, it is possible to eliminate the limitations imposed by hardware. It is possible to easily form any pattern without any trouble.

(3) When forming a pattern, it is logical to use a series of logical value transition information indicating the transition state of the logical value and transition time information indicating the change timing of the logical value in the logical value transition information. This makes it possible to obtain logical value transition information and transition time information without significantly changing the logical simulation results, which have a format that expresses changes in events according to the flow of time. can be linked to LSI testing.

(4) From the above effect (3), TA of semiconductor integrated circuit
This can contribute to shortening T.

(5) By configuring the pattern generation unit by unitizing logical value transition information and transition time information for each input test sequence or output expected value sequence for the LSI under test, only the necessary signal patterns can be generated from other Can be easily changed without affecting the signal pattern. As a result, even in situations where the number of external terminals increases as semiconductor integrated circuits become more highly integrated and logic becomes more complex, logic verification can be performed by simultaneously supplying the required test patterns to a large number of external terminals at different timings. can be facilitated.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto, and various changes can be made without departing from the gist thereof.

For example, the logic verification LSI described in the above embodiments can be constructed by mounting a plurality of semiconductor integrated circuit chips on a wiring board. Furthermore, the comparators and time counters included in the test pattern generation section may be replaced with timers.Furthermore, in the above embodiment, the test pattern is directly supplied to the LSI under test, and the output response of the LSI under test is directly received. Although the explanation is that the voltage is supplied to the comparison/judgment section, in reality, a pin electronics section including a driver that applies a predetermined voltage amplitude to the test pattern is interposed, and such a pin electronics section is connected to logic Verification L
It can be placed outside the SI or built into the LSR.

In the above explanation, the invention made by the present inventor was mainly applied to the generation of test patterns and expected value patterns for logic verification and verification of LSI, which is the field of application that formed the background of the invention. The present invention is not limited thereto, and can be applied to various pattern generation techniques such as pulse generators and logic analyzers. The present invention can be applied to conditions where a signal pattern is formed with at least the required logical value and timing.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, a series of logical value transition information indicating a transition state of a logical value and transition time information indicating a change timing of a logical value in the logical value transition information are stored in a storage means in correspondence, and the access interval of the storage means is By adopting a method of sequentially reading logical value transition information while determining the value based on the transition time information read immediately before, the logical value and timing are determined according to the flow of time corresponding to the transition time information. Since a pattern is formed, logical value transition information and transition time information can be programmably changed and stored in a storage means, and the frequency of a clock signal, which is a reference for defining time, can be changed based on the transition time information. By arbitrarily selecting a pattern, an arbitrary pattern can be easily formed without being limited by hardware.

When forming a pattern, it is logical to use a series of logical value transition information indicating the transition state of the logical value and transition time information indicating the timing of change of the logical value in the logical value transition information. Since it is possible to obtain logical value transition information and transition time information without significantly changing the logical simulation results, which have a format that expresses changes in events according to the flow of time, this makes it possible to verify the logic of actual LSIs. This has the advantage that logical simulation results can be easily linked.

Furthermore, due to the above effect, it is possible to shorten the TAT of the semiconductor integrated circuit.

In addition, by configuring the pattern generation section as a unit so as to form an input test series and an output expected value series for each external terminal of the LSI under test, only the necessary signal patterns can be used to influence other signal patterns. Can be easily changed without any hassle.

As a result, even in situations where the number of external terminals increases as semiconductor integrated circuits become more highly integrated and logic becomes more complex, logic verification can be performed by simultaneously supplying the required test patterns to a large number of external terminals at different timings. can be facilitated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a test pattern generating section which is an embodiment of the present invention. FIG. 2 is an explanatory diagram showing an example of the test pattern waveform output from the test pattern generator, and FIGS. 3(A), (B), and (c) are transition time information and logical value transition information that should form a pair, respectively. FIG. 4 is an explanatory diagram showing an example of the results of a logic simulation used to obtain transition time information and logical value transition information. FIG. 5 is a block diagram of a test pattern generator according to another embodiment of the present invention. FIG. 6 is an explanatory diagram showing an example of transition time information and logical value transition information applicable to the test pattern generator shown in FIG. 5, and FIG. 7 is a test pattern generator that is still another embodiment of the present invention. FIG. 8 is an explanatory diagram showing an example of transition time information and logical value transition information applicable to the test pattern generation section shown in FIG. 7; FIG. 9 is a block diagram of the pattern generation device according to the present invention and FIG. 2 is a block diagram showing an example of a logic verification LSI to which the pattern generation method is applied. 1... LSI for logic verification, 2... LSI to be tested, 1
4... Inspection pattern generation section, 14U1 to 14Un...
- Unit of inspection pattern generation section, 15...Expected value pattern generation section, 17...Comparison timing generation circuit, 2
o...Memory, 21...Address counter, 22.
...Comparator, 24...Latch circuit, 25...
Time counter, φQOmp...coincidence detection signal, CLK
...Clock signal, i...Waveform, Ti...Transition time information, Li...Logic value transition information, j...Waveform, T
j... Transition time information, Lj... Logical value transition information, k
...Waveform, Tk...Transition time information, Lk...Logic value transition information, T...Time information in logic simulation results, L...Logic value information in logic simulation results, Ta...Transition Time information, La...logical value transition information, Tit...transition time information, Lit...
- Logical value transition information. Figure (A) (T41 0. +00 0 (7610~110 1 (B) (7530NI OI (77) O~ 111 (T5) ■ Figure Figure

Claims (1)

[Claims] 1. A series of logical value transition information indicating a logical value transition state;
a storage means capable of storing transition time information indicating the change timing of the logical value in the logical value transition information; and an address generating means for reading out the logical transition information and the transition time information from the storage means in association with each other; A pattern generation device comprising: control means for controlling the next address update timing by the address generation means based on the coincidence between the transition time information read from the storage means and the time information measured. 2. A series of logical value transition information indicating the transition state of logical values for forming an input test sequence or an output expected value sequence for each external terminal of a semiconductor integrated circuit, and the change timing of the logical value in the logical value transition information. a storage means capable of storing transition time information shown in FIG. and control means for controlling the next address update timing by the address generation means based on coincidence with time information measured in synchronization with the pattern generation device formed on one semiconductor substrate. 3. A series of logical value transition information indicating a logical value transition state;
a step of storing the logical value transition information in association with transition time information indicating the time of change of the logical value in the storage means; and a step of reading out the logical transition information and the transition time information located at the top address from the storage means. and updating the access address of the storage means to the next address based on the match between the transition time information read from the storage means and the timed time information, and reading the logical transition information and transition time information from the storage means. A pattern generation method including steps. 4. The pattern generation method according to claim 3, further comprising the step of selecting a clock signal frequency serving as a reference for measuring the time information. 5. A series of logical value transition information indicating a logical value transition state;
The logic value transition information is associated with the transition time information indicating the change timing of the logic value, and the logic value transition information is sequentially read from the storage means according to the time interval defined based on the transition time information. A pattern generation method that creates a pattern that follows the change in time.