JPH0666899A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To produce a test mode signal inside an IC by timing for input of two power supply, and to omit a test mode terminal so as to reduce the number of pins of the IC. CONSTITUTION:A semiconductor integrated circuit is provided with a comparator 1 which outputs a power supply voltage detecting signal S1, a comparator 2 which outputs a voltage detecting signal S2, and a delay circuit 3 in which (m) steps of T-type flip-flops F/F, each of which inputs a clock signal CK from a clock terminal TCK to a clock terminal C while inputs the voltage detecting signal S2 to a reset terminal R, and connects its output terminal Q to the clock terminal C of the next step, are connected in cascade so as to output a delay signal S3. The semiconductor integrated circuit is also provided with an OR gate 4 which inputs the signal S1 to one side and inputs the signal S3 to the other side so as to output an OR output signal S4, and an RS flip-flop 5 which inputs the signal S4 to a reset terminal NR, inputs the signal S2 to the set terminal NS, and outputs a test mode signal SN to a test mode node N so as to construct a decision circuit 6 together with the OR gate 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
Particularly, it relates to the test mode setting of the internal circuit.

[0002]

2. Description of the Related Art As shown in FIG. 5, a conventional semiconductor integrated circuit (hereinafter abbreviated as an IC) has two independent power supply voltages V1 and V1 via an internal circuit via power supply terminals T1 and T2, respectively.
V2 is supplied to the internal circuit for operation.

When the operation of this internal circuit is tested as the circuit under test 11, the IC is tested after the two power supply voltages V1 and V2 shown in FIG. 6 reach a steady state in order to shorten the test time. To a test state different from the normal operation state, that is, a test mode.

In order to set the test mode, the test mode signal SM is applied to the dedicated test mode signal input terminal TM and is supplied to the circuit under test 11 via the test mode node N.

[0005]

In the conventional semiconductor integrated circuit, there is a problem that a dedicated test mode terminal is required to test the internal circuit, and the number of IC pins is increased.

An object of the present invention is to provide a semiconductor integrated circuit which does not require a dedicated test mode terminal.

[0007]

In the semiconductor integrated circuit of the present invention, the first and second power supply input terminals are supplied with first and second power supply voltages having different rise times, respectively, to operate the internal circuit. In the test mode, in the semiconductor integrated circuit in which the test mode signal is supplied to the circuit under test through the test mode node, the first and second semiconductor integrated circuits are provided.
First and second power supply voltage detection circuits that detect when the power supply voltages of the respective power supply voltages have reached predetermined reference voltage values and output corresponding first and second power supply voltage detection signals, and the second power supply. A delay circuit for delaying the voltage detection signal for a predetermined time,
A determination circuit for determining the context between the output time of the first power supply voltage detection signal and the predetermined time delay time is added,
The rising time of the first power supply voltage detection signal is controlled to supply the test mode signal to the test mode node.

[0008]

The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention. In the semiconductor integrated circuit of this embodiment, the test mode signal generation circuit 10a is inserted between the conventional first and second power supply terminals T1 and T2 and the clock terminal TCK and the test mode contact N, and the test mode signal input terminal is inserted. The semiconductor integrated circuit is similar to the conventional semiconductor integrated circuit except that the TM is removed.

The test mode signal generating circuit 10a has a positive input end connected to the first power supply terminal T1 and a negative input end connected to the reference voltage E1 and outputs a power supply voltage detection signal S1.
From the clock terminal TCK to the clock terminal C of the comparator 1 and the second comparator 2 whose positive input end is connected to the second power supply terminal T2 and whose negative input end is connected to the reference voltage E2 and which outputs the voltage detection signal S2. The clock signal CK is input, the voltage detection signal S2 is input to the reset end R, and the output end Q
Is a delay circuit 3 in which T-type flip-flops F / F connected to the clock terminal C of the next stage are cascade-connected in m stages to output a delay signal S3, and the first power supply voltage detection signal S1 is input to one side and delayed to the other side. An OR gate 4 which receives the signal S3 and outputs an OR output signal S4, an OR output signal S4 at the reset end NR, and a second power supply voltage detection signal S2 at the set end NS.
To input the most mode signal SN to the most mode node N.
Which forms the decision circuit 6 together with the OR gate 4
It has a flip-flop 5.

Here, the delay circuit 3 and the judging circuit 6 constitute a delay judging circuit 9a. 2A to 2C are timing charts of respective signals for explaining the operation of the circuit of FIG. First, referring to FIG. 2A, the waveform of the detection signal S2 output from the second comparator 2 will be described. When the potential V2 of the second power supply terminal T2 is equal to or lower than the reference voltage E2, the power supply voltage detection signal S2 is "L". This is the level, and the detection signal S2 becomes "H" level from the time t1 when the voltage becomes equal to or higher than the voltage E2.

Here, the delay signal S3 is converted into m of the clock signal CK by the delay circuit 3 of m T-type flip-flops.
The waveform becomes a frequency-divided waveform, and becomes "L" level at time tm, which is a period τm after time t1.

FIG. 2B shows the OR gate 4 corresponding to the waveform S1f when the time tf when the power supply voltage detection signal S1 of the comparator 1 rises to the "L" level is earlier than the falling time tm of the delay signal S3. The waveforms of the OR output signal S4 and the test mode signal SN output from the determination circuit 6 are shown.

In this case, the OR output signal S4 is always "H".
Since it is at the level, the RS flip-flop 5 is not set and the test mode signal SN is always at the "H" level.

Test circuit 1 via test mode node N
When the test mode signal SN input to 1 is "H" level, normal operation is performed, and when the test mode signal SN is "L" level, the test mode signal SN is entered. Therefore, by setting the timing of the power supply voltage V1 and the power supply voltage V2, You can also control the mode.

In FIG. 2C, the time t at which the power supply voltage V2 rises late and the power supply voltage detection signal S1 is later than the time tm.
It is a waveform of the OR output signal S4 and the test mode signal SN in the case of the waveform S1S of s.

In this case, the OR output signal S4 changes from the time point tm to.
There is a period during which it becomes the "L" level during ts. Therefore, the RS flip-flop 5 is set, the test mode signal SN is held at the "L" level from the time tm, and the test mode is set.

In general, when the IC is operated by the two power sources, the rise time of each of the two power sources usually differs by several tens to several hundreds of msec. Even in such a case, the test mode is mistakenly set to about 1 second.

As described in the present embodiment, the circuit under test 11 in the IC can be put into the test mode by using the timing difference between the rise times of the two power supply voltages. Therefore, the conventional test mode signal shown in FIG. The terminal TM becomes unnecessary and the number of pins can be reduced by one.

FIG. 3 is a circuit diagram of the second embodiment of the present invention. The circuit configuration for generating the power supply voltage signals S1 and S2 is similar to that of the first embodiment shown in FIG.

Test mode signal generation circuit 10 of this embodiment
The delay circuit 9b of b receives the second power supply voltage detection signal S2 and the NAND gate 7 for inputting the signal SC for delaying the second power supply voltage detection signal S2 for a predetermined time by CR, and the output signal S7 thereof for input to the clock terminal C and the data terminal. The first power supply voltage detection signal SI is input to D, the detection signal S2 is input to the reset end R, and the test mode signal SN is input from the output end Q to the test mode node N.
It has a T-type flip-flop 8 for outputting to.

FIGS. 4A to 4C are timing charts of respective signals for explaining the operation of the circuit of FIG. When the CR delay signal SC shown in FIG. 4A reaches the threshold voltage Vth of the NAND gate 7 at time tTH, FIG.
As shown in (b) and (c), the first power supply voltage detection signal S1 includes the signal S1f at the early time point tf and the signal S1S when it is late, and the same operation as that of the first embodiment described in FIG. Is effective. The present embodiment is somewhat inferior in the stability of the set time tTH, but has an advantage that the number of parts is smaller than that of the circuit of the first embodiment.

[0022]

As described above, the present invention is provided with the test mode signal generation circuit having the two-system voltage detection circuits having different rising edges and the delay / judgment circuit. The test mode signal can be generated internally, and the effect of reducing the number of pins of the IC by omitting the test mode terminal is provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a timing chart of each signal for explaining the operation of the circuit of FIG.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

4 is a timing chart of each signal for explaining the operation of the circuit of FIG.

FIG. 5 is a circuit diagram of an example of a conventional semiconductor integrated circuit.

FIG. 6 is a timing chart of signals for explaining the operation of the circuit of FIG.

[Explanation of symbols]

 1, 2 Comparator 3 Delay Circuit 4 OR Gate 5 RS Flip-Flop 6 Judgment Circuit 7 NAND Gate 8 D-Type Flip-Flop 9, 9a Delay Judgment Circuit 10, 10a Test Mode Signal Generation Circuit 11 Tested Circuit T1, T2 First, First 2 power supply input terminal TCK clock signal terminal V1, V2 first and second power supply voltage S1f normal mode setting signal S1S test mode setting signal SN test mode signal S1, S2 first and second power supply voltage detection signal S3 delay element S4 OR output signal N Test mode node E1, E2 Reference voltage CK Clock signal τm Setting period t1, t2, tm, ts

Claims (1)

[Claims] 1. A first and a second power supply input terminals are supplied with first and second power supply voltages having different rise times, respectively, to operate an internal circuit, and in a test mode, a voltage is supplied via a test mode node. In a semiconductor integrated circuit in which a test mode signal is supplied to the circuit which is a test circuit,
And first and second power supply voltage detection circuits that detect the time when the second power supply voltage has reached a predetermined reference voltage value and output corresponding first and second power supply voltage detection signals, respectively. A delay circuit for delaying the power supply voltage detection signal of No. 2 for a predetermined time, and a judgment circuit for judging the front-back relation between the output time of the first power supply voltage detection signal and the predetermined time delay time are added, and the first circuit is added. A semiconductor integrated circuit, characterized in that the rising time of a power supply voltage detection signal is controlled to supply the test mode signal to the test mode node.