JP3516727B2 - Logical comparator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logical comparator for performing classification based on a difference in signal output time with respect to an input signal of a device under test. 2. Description of the Related Art As shown in FIG. 3, when an input signal is applied to a device under test (DUT) 10 in a basic period T, each DUT 10 has a delay which varies with respect to the input signal for each device. Generate an output signal with time. Therefore,
The DUT 10 may be classified according to the width of the delay time. Here, for a certain input signal, the output signal changes from H level to L level, and the change points are DUT1 during time T1, DUT2 during time T2, DUT3 during time T3, DUT during time T4
Suppose there are four. Conventionally, the circuit shown in FIG. 4 has been used to distinguish the difference in the output time. The conventional circuit shown in FIG. 4 includes a level comparator 11 that determines the H level and the L level of the DUT 10 output signal Dout, and a gate that controls a signal output from the level comparator 11 with a comparison control signal that enables timing comparison. Signal (STROB)
, A timing comparator 12 for detecting whether the output of the gate is H level or L level, a timing generator 13 for generating STROB, an expected value level comparator for comparing an output signal of the timing comparator 12 with an expected value 14. A comparison result holding circuit 15 for holding the result of comparison with the expected value level at the end of the STROB signal. FIG. 5 shows that, for a certain input signal, the output signal changes from H level to L level, and the point of change is time T
2 is a test timing chart for DUT2 located between the two. The output Dout of the DUT2 changes from the H level to the L level during the time T2. The output Dout is compared with the comparison voltage VO by the level comparator 11, and changes from the H level to the L level after being delayed by the propagation delay time of the level comparator 11. STR which is the output of the timing generator 13
In the first basic cycle T, OB changes from the L level to the H level at the rear end of the time T1, and changes from the H level to the L level at the rear end of the first basic cycle T. STRO
At the rise of B, the clear terminal of the flip-flop in the timing comparator 12 is at the H level because the output of the level comparator 11 and the comparison control signal are at the H level, and the output of the flip-flop, ie, the timing comparator 1
The output of 2 holds the H level. In this example, the expected value is at the L level, and the output of the expected value level comparator 14 is at the H level.
At the H level. Since the comparison result H level indicates a disagreement with the expected value, the result is FAIL in this case. In the second basic cycle T, the STR
OB changes from the L level to the H level at the rear end of the time T2, and changes from the H level to the L level at the rear end of the second basic cycle T. At the rise of the STROB, the clear terminal of the flip-flop in the timing comparator 12 is at the L level because the output of the level comparator 11 is at the L level and the comparison control signal is at the H level. The output of the detector 12 changes from H level to L level. The expected value is at the L level, and the output of the expected value comparator 14 is at the L level.
At the end of OB, the comparison result holding circuit 15 holds L level. Since the comparison result L level indicates agreement with the expected value, PASS is obtained in this case. In the third basic period T, STR
OB changes from the L level to the H level at the rear end of the time T3, and changes from the H level to the L level at the rear end of the third basic cycle T. At the rise of STROB, the clear terminal of the flip-flop in the timing comparator 12
The L level is the same as the first basic cycle T,
The output of the timing comparator 12 changes from H level to L level. Since the output of the expected value level comparator 14 becomes L level, the comparison result holding circuit 15 holds L level at the rear end of the STROB. Since the comparison result L level indicates agreement with the expected value, PASS is obtained in this case. In the fourth basic cycle T, STR
OB changes from the L level to the H level at the rear end of the time T4, and changes from the H level to the L level at the rear end of the fourth basic cycle T. At the rise of STROB, the clear terminal of the flip-flop in the timing comparator 12
The L level is the same as the first basic cycle T,
The output of the timing comparator 12 changes from H level to L level. Since the output of the expected value level comparator 14 becomes L level, the comparison result holding circuit 15 holds L level at the rear end of the STROB. Since the comparison result L level indicates agreement with the expected value, PASS is obtained in this case. DUT1 has a transition point of the output signal from H level to L level during time T1, DUT3 is during time T3, and DUT4 is during time T4. In the third and fourth basic periods T, the following test results can be obtained, respectively.
Classification can be performed according to the difference in the signal output time of T10. DUT1 DUT2 DUT3 DUT4 First pass PASS FAIL FAIL FAIL Second pass PASS PASS FAIL FAIL Third pass PASS PASS PASS FAIL Fourth pass PASS PASS PASS PASS Executes the basic cycle T several times and repeats ST
The rising timing of the ROB is changed, and the classification based on the difference in the signal output time of the DUT 10 is performed based on the comparison result each time. If attention is paid only to this part of the test, in the case of the above-mentioned conventional example, T × 4 time is required for classification. As described above, in the conventional circuit, when the classification based on the difference in the signal output time of the DUT is attempted, the STR
It is necessary to execute the test several times by changing the OB generation timing, and there is a disadvantage that the test time increases. SUMMARY OF THE INVENTION It is an object of the present invention to realize a logical comparator that performs classification based on a difference in signal output time with respect to an input signal of a device under test in a short test time. In order to achieve the above object, according to the present invention, in a classification based on a difference in signal output time with respect to an input signal of a device under test, a timing for generating a plurality of comparison timing signals is provided. A generator is provided. Each of the comparison timing signals is input to a respective clock terminal, and the output of the device under test is passed through a level comparator and a gate controlled by a comparison control signal, and is input to a clear terminal. A timing comparator is provided. Then, a plurality of expected value level comparators for comparing outputs of the plurality of flip-flops with expected values are provided. The outputs of the plurality of expected value level comparators are held in the plurality of comparison result holding circuits at the end of the comparison timing signal. In the logical comparator configured as described above, the number of classifications based on the difference in the signal output time with respect to the input signal can be arbitrarily set by increasing or decreasing the expandable unit. In the logical comparison circuit configured as described above, a plurality of comparison timing signals are generated during one basic cycle T, and classification based on a difference in a plurality of signal output times with respect to an input signal is performed. it can. Therefore, assuming that the number of classifications is N, there is an effect of reducing the classification time to 1 / N as compared with the conventional circuit. As shown in FIG. 3, in a basic period T, D
When an input signal is applied to the UT 10, the output signal of the DUT 10 changes from the H level to the L level, and the change point is between the DUT 1 during the time T1 and the DU during the time T2.
It is assumed that there is a DUT3 between T2 and time T3 and a DUT4 between time T4. In the present invention, the circuit shown in FIG. 1 is used to distinguish the difference between the output times. The circuit of FIG.
The UT 10 includes a level comparator 11 that determines the H level and the L level of the output signal Dout, and a gate that controls a signal output from the level comparator 11 with a comparison control signal that enables timing comparison, and includes a comparison timing signal (STROB1, STROB).
(ROB2, STROB3, STROB4), the timing comparator 22, which detects whether the output of the gate is H level or L level at each comparison timing, the timing generator 23 which generates a comparison timing signal, and the timing comparator 22 An expected value level comparator 14 for comparing the output signal with the expected value, and a comparison result holding circuit 15 for holding the result of the comparison with the expected value level at the end of the comparison timing signal. FIG. 2 shows that, for a certain input signal, the output signal changes from H level to L level and the point of change is time T
2 is a test timing chart for DUT2 located between the two. The output Dout of the DUT2 changes from the H level to the L level during the time T2. The output Dout is compared with the comparison voltage VO by the level comparator 11, and changes from the H level to the L level after being delayed by the propagation delay time of the level comparator 11. STR which is the output of the timing generator 23
OB1 changes from L level to H level at the end of time T1, and changes from H level to L level at the end of basic period T. At the rise of STROB1, the clear terminal of the flip-flop F / F1 in the timing comparator 22 is at the H level because the output of the level comparator 11 and the comparison control signal are at the H level, and the output of the F / F1 is at the H level. Hold the level. In the present embodiment, the expected value is at the L level, and the output of the expected value level comparator 14 is at the H level. Therefore, the H level is held in the comparison result holding circuit 15 at the rear end of STROB1. Since the H level of the comparison result 1 indicates disagreement with the expected value, the result is FAIL in this case. Subsequently, STROB2, which is the output of the timing generator 23, changes from L level to H at the end of time T2.
The level changes from H level to L level at the end of the basic period T. At the rise of STROB2, the clear terminal of the flip-flop F / F2 in the timing comparator 22 is at L level because the output of the level comparator 11 is at L level and the comparison control signal is at H level.
The output of F2 changes from H level to L level. In the present embodiment, the expected value is at the L level, and the output of the expected value level comparator 14 is at the L level, so that the comparison result holding circuit 15 holds the L level at the rear end of STROB2.
Since the L level of the comparison result 2 indicates a match with the expected value, PASS is obtained in this case. Subsequently, STROB3, which is the output of the timing generator 23, changes from L level to H at the end of time T3.
The level changes from H level to L level at the end of the basic period T. At the time of rising of STROB3, the clear terminal of the flip-flop F / F3 in the timing comparator 22 is set in the same manner as at the time of rising of STROB2.
It is at L level, and the output of F / F3 changes from H level to L level. In the present embodiment, the expected value is at the L level, and the output of the expected value level comparator 14 is at the L level.
5 holds the L level. Since the L level of the comparison result 3 indicates a match with the expected value, the result is PASS in this case. Subsequently, STROB4, which is the output of the timing generator 23, changes from the L level to the H level at the end of the time T4.
The level changes from H level to L level at the end of the basic period T. At the time of rising of STROB4, the clear terminal of the flip-flop F / F4 in the timing comparator 22 is set in the same manner as at the time of rising of STROB2.
It is at L level, and the output of F / F4 changes from H level to L level. In the present embodiment, the expected value is at the L level, and the output of the expected value comparator 14 is at the L level.
5 holds the L level. Since the L level of the comparison result 4 indicates a match with the expected value, the result is PASS in this case. DUT1 has a transition point of the output signal from H level to L level during time T1, DUT3 is during time T3, and DUT4 is between time T4. 2, the following test results can be obtained for the comparison results 3 and 4, respectively. For this reason, the classification based on the difference in the signal output time of the DUT 10 becomes possible in one basic cycle T. DUT1 DUT2 DUT3 DUT4 Comparison result 1 PASS FAIL FAIL FAIL Comparison result 2 PASS PASS FAIL FAIL Comparison result 3 PASS PASS PASS FAIL Comparison result 4 PASS PASS PASS PASS We do classification by time difference,
By increasing or decreasing the number of expandable units 30, any number N can be classified, and the classification time can be reduced to 1 / N as compared with a conventional circuit. The present invention is configured as described above. Therefore, when the number of expandable units is N, the classification based on the difference in the signal output time with respect to the input signal is performed in the conventional circuit. The time can be reduced to 1 / N of the time, which is effective for reducing the test time.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a logical comparison circuit according to the present invention. FIG. 2 is a timing chart in the embodiment of the present invention. FIG. 3 is a timing chart showing an example of an input signal and an output signal of a device under test. FIG. 4 is a block diagram of a conventional logic comparison circuit. FIG. 5 is a timing chart in a conventional logic comparison circuit. [Description of Signs] 10 Device under test (DUT) 11 Level comparator 12, 22 Timing comparator 13, 23 Timing generator 14 Expected value level comparator 15 Comparison result holding circuit 30 Expandable unit

Claims (1)

(57) [Claim 1] In a classification based on a difference in signal output time with respect to an input signal of a device under test (10), a timing generator (23) for generating a plurality of comparison timing signals is provided. A plurality of flip-flops for inputting each of the above-mentioned comparison timing signals to a terminal, inputting the output of the device under test (10) to another terminal through a level comparator (11) and a gate controlled by a comparison control signal A plurality of expected value level comparators (14) for comparing outputs of the plurality of flip-flops with expected values; and providing a plurality of expected value level comparators (14). A logical comparator, comprising: a plurality of comparison result holding circuits (15) for holding the outputs of (1) and (2).