KR20020020551A - Apparatus for pulse sequence generation using Shift Register - Google Patents

Abstract

PURPOSE: A pulse train generator using a shift register is provided to generate a single pulse having a width of T and a pulse train having a period of N(N-1) using an N bit shift register and (N-1) bit shift register. CONSTITUTION: A bit shift controller(31,32,33,34) designates a shift start location of an external pulse train. A first D-flip flop(31) receives a reference clock and an input pulse. A second D-flip flop(32) receives a non-inverting output of the first D-flip flop(31) and a logic 1 through clock and input terminals thereof, respectively. An inverter(33) inverts a non-inverting output of the second D-flip flop(32). A first AND gate(34) ANDs an output of the inverter(33) and a non-inverting output of the first D-flip flop(31). A bit shift section(35,36,37,38,39) bit-shifts the external pulse train from the shift start location and generates a pulse train having a predetermined period. A first OR gate(35) ORs an output of the first AND gate(34) and an output of an (N-1) bit shift register(37). A second OR gate(36) ORs an output of the AND gate(34) and an output of an N bit shift register(38). The (N-1) bit shift register(37) receives an output of the first OR gate(35) and a reference clock. The N bit shift register(38) receives an output of the second OR gate(36) and the reference clock. A second AND gate(39) ANDs outputs of the (N-1) bit shift register(37) and N bit shift register(38).

Description

Pulse train generator using shift register {Apparatus for pulse sequence generation using Shift Register}

TECHNICAL FIELD The present invention relates to a pulse string generating apparatus, and in particular, using a N bit shift register and an N-1 bit shift register, a period from a pulse string having a pulse width of T or a pulse string having an arbitrary period is N (N-1). The present invention relates to a pulse train generator using a shift register suitable for generating a pulse train of T.

In general, pulse trains are used as various control signals or reference signals in digital circuits.

The prior art for generating such a pulse train will be described.

First, FIG. 1 is a block diagram of a pulse train generator according to the prior art, and FIG. 2 is a signal timing diagram of each device of FIG.

Conventionally, a clock division circuit for dividing a reference clock into a low speed clock having an appropriate period is used.

That is, in the pulse string generator configured as shown in FIG. 1, the clock input by using the clock divider 10 is divided. The clock divider 10 may be variously applied according to an operating environment. In FIG. 1, the clock divider 10 is representatively illustrated.

The clock division of the clock division stage 10 is performed by a plurality of D-flip flops 11 and 12.

Therefore, the pulse train generator generates inverted outputs of the reference clock CLK and the second D flip-flop 12. A first D-flip flop 11 receiving the clock terminal C and the input terminal D, respectively; A second D flip-flop 12 which receives the non-inverting output Q of the reference clock CLK and the first D flip-flop 11 through the clock terminal C and the input terminal D, respectively; A third D flip-flop 21 which receives the non-inverting output Q of the reference clock CLK and the second D flip-flop 12 through the clock terminal C and the input terminal D, respectively; A fourth D flip-flop 22 which receives the reference clock CLK and the non-inverting output Q of the third D flip-flop 21 through the clock terminal C and the input terminal D, respectively; A logic gate 23 which receives the non-inverting output Q of the third D-flip flop 21 and the non-inverting output Q of the fourth D-flip flop 22 and performs an exclusive OR operation (XOR); The fifth D-flip flop 24 receives the output of the logic gate 23 according to the reference clock CLK input to the clock terminal and outputs the pulse string PS through the non-inverting output terminal Q. .

The third D-flip flop 21 and the fifth D-flip flop 24 are for retiming the divided clock and the pulse train, respectively.

The operation of the device configured as described above will be described in detail.

First, the reference clock CLK is input to the clock terminals of each of the D-flip flops 11, 12, 21, 22, and 24.

2 shows the timing of each signal for the pulse train generation process. In FIG. 2, the reference clock CLK is A1.

Then, the non-inverting output Q of the first D flip-flop 11 is input to the input terminal of the second D flip-flop 12, and the inverting output of the second D flip-flop 12 is formed. ) Is fed to the input terminal of the first D-flip flop (11). The converted signal is delayed by two clocks of the reference clock A1 by the first D-flip-flop 11 and the second D-flip-flop 12, and then is applied to the output of the second D-flip-flop 12 again. It is reflected.

The clock divider 10 divides the reference clock A1 into four and outputs the same through the non-inverting terminal Q of the second D-flip flop 12.

The clock A2 divided by the clock division stage 10 is retimed to the reference clock by the third D flip-flop 21 to become A3. A3 is input to the input terminal D of the logic gate 23 and the fourth D-flop flop 22.

The fourth D-flip-flop 22 outputs A4 by delaying A3 by a reference clock period.

The A4 output from the fourth D-flop flop 22 and the re-timed A3 of the third D-flop flop 21 are input to the logic gate 23 to perform an exclusive OR operation, so that the period is four times the reference clock. The pulse string A5 is output.

The A5 output from the logic gate 23 is retimed to the reference clock A1 by the fifth D-flop flop 24 and then output as A6, which is the final pulse string PS, through the non-inverting terminal Q. .

However, the conventional apparatus described above has a disadvantage in that the circuit of the clock division stage is complicated and a large number of flip-flops are required when the period of the finally generated pulse string is much larger than the reference clock.

For example, to generate an 8 kHz pulse train from a high-speed 51.84 MHz reference clock, the reference clock must be divided by 6480, which requires 3240 D-flip flops for clock division.

Therefore, it was difficult to apply the conventional apparatus to an environment that generates a low speed pulse train from a high speed reference clock.

Accordingly, the present invention has been proposed to solve the conventional problems as described above, and an object of the present invention is to provide a pulse width using an N-bit shift register and an N-1 bit shift register in a pulse train generator. The present invention provides a pulse train generator using a shift register suitable for generating a pulse train having a period N (N-1) T from a single pulse of T or a pulse train having an arbitrary period.

In order to achieve the above object, a pulse train generation apparatus using a shift register according to the present invention includes a bit shift control stage for designating a shift start position of an externally supplied pulse train; A technical feature of the present invention is that the bit shift stage is configured to bit shift the pulse train from a shift start position designated by the bit shift control stage to generate a pulse train of a predetermined period.

1 is a block diagram of a pulse train generator according to the prior art,

2 is a timing diagram of each signal of the apparatus according to FIG. 1;

3 is a block diagram of a pulse train generator using a shift register according to an embodiment of the present invention;

4 is a timing diagram of each signal of the apparatus shown in FIG.

Explanation of symbols on the main parts of the drawings

31, 32, 40: D-flip-flop 33: Logic negative gate

34, 39: AND gate 35, 36: AND gate

37, 38: shift register

Hereinafter, the configuration and operation of the present invention will be described based on the embodiment according to the technical idea of the pulse train generating apparatus using the shift register as described above.

First, FIG. 3 is a block diagram of a pulse train generator using a shift register according to an exemplary embodiment of the present invention, and FIG. 4 is a signal timing diagram of the device of FIG.

As shown in FIG. 3, a preferred embodiment of the present invention includes a first D− that receives a reference clock CLK and an input pulse PULSE in the case of the bit shift control stages 31, 32, 33, and 34. Flip-flop 31; A second D flip-flop 32 which receives the non-inverting output Q and logic 1 of the first D flip-flop 31 as a clock terminal and an input terminal, respectively; A logic negative gate 33 for inverting the non-inverting output Q of the second D flip-flop 32; A first AND gate 34 for performing an AND operation on the output of the logic negation gate 33 and the non-inverting output Q of the first D flip-flop 31,

In the case of the bit shift stages 35, 36, 37, 38, and 39, the first logical sum gate that receives the output of the first AND gate 34 and the output of the N−1 bit shift register 37 and performs an OR operation. 35); A second AND gate 36 for receiving the output of the first AND gate 34 and the output of the N bit shift register 38 and performing an OR operation; An N-1 bit shift register 37 for receiving an output of the first AND gate 35 and a reference clock CLK; An N bit shift register 38 for receiving an output of the second OR gate 36 and a reference clock CLK; A second AND gate 39 for ANDing the outputs of the N-1 bit shift register 37 and the N bit shift register 38,

The output of the second AND gate 39 is retimed according to the reference clock CLK to form a third D flip-flop 40 that outputs the final pulse string PS.

Referring to the operation of the device according to such a configuration as follows.

According to the present invention, a shift register is used without using a clock division stage, so that a circuit configuration for clock division is not complicated even when the period of the pulse string becomes very large compared to the reference clock.

Thus, the apparatus proposed by the present invention uses a pulse of which the pulse width is the same as the period of the reference clock or a pulse string of any period equal to the period of the reference clock without using a clock divided with the reference clock.

Also, an N bit shift register and an N-1 bit shift register are used. In this case, since N and N-1 are prime factors, the least common multiple is N (N-1).

4 shows a timing diagram when N = 3 and a pulse train of an arbitrary period is input.

In FIG. 4, the reference clock is B1 and the input pulse train PULSE is equal to B2. In this case, the input pulse string PULSE may be a single pulse having the same period as that of the reference clock or may be any pulse string having a different period. Here, a case where an arbitrary pulse string is input will be described.

The input pulse train B2 is retimed to the reference clock B1 by the first D-flip flop 31 and output to the second D-flip flop 32 and the first AND gate 34 as B3. do.

Then, B4 input to the input terminal of the second D flip-flop 32 is inverted from logic 1 to logic 0 through the logic negating gate 33 when the first falling edge of the retimed B3.

B4, which has been inverted to logic 0, will continue to be in that state. Therefore, the output B5 of the first AND gate 34 becomes logic 1 only during the first pulse of B3 retimed in the first D-flip-flop 31.

For this reason, the same operation result can be obtained even when a single pulse is input instead of a pulse train.

The outputs of the N-1 bit shift register 37 and the N bit shift register 38 are equal to B6 and B7, respectively. At this time, it can be seen that B6 and B7 become logic 1 at every six reference clocks.

B6 and B7, which are the outputs of the N-1 bit shift register 37 and the N bit shift register 38, are input to the second AND gate 39 and the result of the OR operation is the same as B8.

The output B8 of the second AND gate 39 becomes a pulse train whose period is six times the reference clock B1, and this B8 is retimed by the third D-flip flop 40 according to the reference clock B1. It becomes like B9.

B9 is the final pulse train PS, which is the final output of the pulse train generator according to the present invention.

On the other hand, even if it is not N as described above and the operation principle is the same.

In addition, when input of a single pulse or an arbitrary period of pulse trains is not available, in the initial state, each of the two shift registers 37 and 38 loads a value in which only one of the most significant bits is logic 1 and all other bits are logic 0. Thus, a pulse train whose period is N (N-1) times the reference clock period can be generated.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the pulse string generator using the shift register according to the present invention can be configured with a simpler device than the case of using a clock divider circuit composed of a plurality of D-flip flops when generating a pulse string from a high-speed reference clock. There are advantages to it.

That is, the number of gates can be reduced when designing an apparatus for generating a pulse train, and the synchronous optical transmission system can easily generate various pulse trains required for system control from frame pulses.

In addition, it is possible to generate a pulse train of various cycles by accommodating a single pulse or an arbitrary cycle of pulse trains in one device, and the N-1 bit shift register and the N bit shift register can be generated even in a system without a single pulse or an arbitrary cycle pulse train. There is an effect that can generate a pulse train having a period of N (N-1) times the reference clock period.

In addition, the apparatus according to the present invention can be applied to FPGAs and the like in the E1T1U being developed.

Claims (6)

In the apparatus for generating a pulse train of a certain period from the reference clock, A bit shift control stage for designating a shift start position of an externally supplied pulse train; And a bit shift stage configured to bit shift the pulse sequence from a shift start position designated by the bit shift control stage, thereby generating a pulse sequence of a predetermined period. According to claim 1, wherein the externally supplied pulse train, Pulse train having a random period or a pulse train generator using a shift register, characterized in that a single pulse of the same period as the reference clock. The method of claim 1, wherein the bit shift control stage, A first D flip-flop for retiming the input pulse train according to the reference clock; A second D-flip-flop and logic negative gate receiving logic 1 and inverting the re-timed pulse train at a predetermined position to output logic 0; And a logical AND gate that specifies a shift start position as a result of performing an AND operation on the pulse string output from the first D-flip flop and the logic 0 output from the second D-flip flop and the logic negation gate. Pulse train generator using a shift register characterized in that. The method of claim 1, wherein the bit shift stage, With a plurality of shift registers, the pulse string generated by shifting the input pulses by N bits and N-1 bits, respectively, from the shift start position designated by the bit shift control stage results in an N (N-1) times period of the reference clock. Pulse train generator using a shift register characterized in that it has. The method of claim 1, wherein the bit shift stage, A plurality of shift registers are provided so that the number of bits to be shifted to each other is small and the output of the shift registers is logically generated to generate a pulse sequence. Pulse train generator using a shift register, characterized in that to have a period corresponding to the product of. The method of claim 4, wherein the bit shift stage, A first OR gate receiving the output of the bit shift control stage and the output of the N-1 bit shift register and performing an OR operation; A second OR gate receiving the output of the bit shift control stage and the output of the N bit shift register and performing an OR operation; An N-1 bit shift register configured to shift the output of the first AND gate by N-1 bits according to a reference clock; An N bit shift register configured to shift the output of the second AND gate by N bits according to a reference clock; And a logical AND gate for performing an AND operation on the outputs of the N-1 bit shift register and the N bit shift register.