JPS6039846A - 半導体集積回路装置の製造方法 - Google Patents

半導体集積回路装置の製造方法

Info

Publication number
JPS6039846A
JPS6039846A JP58148057A JP14805783A JPS6039846A JP S6039846 A JPS6039846 A JP S6039846A JP 58148057 A JP58148057 A JP 58148057A JP 14805783 A JP14805783 A JP 14805783A JP S6039846 A JPS6039846 A JP S6039846A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
oxidation
resistant mask
groove
mask layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58148057A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6348180B2 (enExample
Inventor
Akira Kawakatsu
川勝　章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP58148057A priority Critical patent/JPS6039846A/ja
Priority to US06/638,942 priority patent/US4582565A/en
Publication of JPS6039846A publication Critical patent/JPS6039846A/ja
Publication of JPS6348180B2 publication Critical patent/JPS6348180B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/041—Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/40—Isolation regions comprising polycrystalline semiconductor materials

Landscapes

  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Local Oxidation Of Silicon (AREA)
JP58148057A 1983-08-15 1983-08-15 半導体集積回路装置の製造方法 Granted JPS6039846A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP58148057A JPS6039846A (ja) 1983-08-15 1983-08-15 半導体集積回路装置の製造方法
US06/638,942 US4582565A (en) 1983-08-15 1984-08-08 Method of manufacturing integrated semiconductor circuit devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58148057A JPS6039846A (ja) 1983-08-15 1983-08-15 半導体集積回路装置の製造方法

Publications (2)

Publication Number Publication Date
JPS6039846A true JPS6039846A (ja) 1985-03-01
JPS6348180B2 JPS6348180B2 (enExample) 1988-09-28

Family

ID=15444203

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58148057A Granted JPS6039846A (ja) 1983-08-15 1983-08-15 半導体集積回路装置の製造方法

Country Status (2)

Country Link
US (1) US4582565A (enExample)
JP (1) JPS6039846A (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61228650A (ja) * 1985-04-02 1986-10-11 Sony Corp 半導体装置の製造方法
JPS61229339A (ja) * 1985-04-04 1986-10-13 Fujitsu Ltd 半導体装置
JPS63186472A (ja) * 1987-01-28 1988-08-02 Mitsubishi Electric Corp 半導体集積回路装置およびその製造方法
JPH02158134A (ja) * 1988-12-12 1990-06-18 Sony Corp 半導体装置の製造方法

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4656497A (en) * 1984-11-01 1987-04-07 Ncr Corporation Trench isolation structures
US4983226A (en) * 1985-02-14 1991-01-08 Texas Instruments, Incorporated Defect free trench isolation devices and method of fabrication
JPS61258468A (ja) * 1985-05-13 1986-11-15 Hitachi Ltd 半導体記憶装置およびその製造方法
US4674173A (en) * 1985-06-28 1987-06-23 Texas Instruments Incorporated Method for fabricating bipolar transistor
US4767722A (en) * 1986-03-24 1988-08-30 Siliconix Incorporated Method for making planar vertical channel DMOS structures
US4666556A (en) * 1986-05-12 1987-05-19 International Business Machines Corporation Trench sidewall isolation by polysilicon oxidation
JPS63122261A (ja) * 1986-11-12 1988-05-26 Mitsubishi Electric Corp 半導体装置の製造方法
US4755477A (en) * 1987-03-24 1988-07-05 Industrial Technology Research Institute Overhang isolation technology
US4870029A (en) * 1987-10-09 1989-09-26 American Telephone And Telegraph Company, At&T-Technologies, Inc. Method of forming complementary device structures in partially processed dielectrically isolated wafers
US4855804A (en) * 1987-11-17 1989-08-08 Motorola, Inc. Multilayer trench isolation process and structure
US4871689A (en) * 1987-11-17 1989-10-03 Motorola Inc. Multilayer trench isolation process and structure
US4876217A (en) * 1988-03-24 1989-10-24 Motorola Inc. Method of forming semiconductor structure isolation regions
US5021852A (en) * 1989-05-18 1991-06-04 Texas Instruments Incorporated Semiconductor integrated circuit device
US5433794A (en) * 1992-12-10 1995-07-18 Micron Technology, Inc. Spacers used to form isolation trenches with improved corners
US5989977A (en) * 1998-04-20 1999-11-23 Texas Instruments - Acer Incorporated Shallow trench isolation process
US6602759B2 (en) 2000-12-07 2003-08-05 International Business Machines Corporation Shallow trench isolation for thin silicon/silicon-on-insulator substrates by utilizing polysilicon
US8649123B1 (en) 2008-11-26 2014-02-11 Western Digital (Fremont), Llc Method to eliminate reactive ion etching (RIE) loading effects for damascene perpendicular magnetic recording (PMR) fabrication
US8257597B1 (en) 2010-03-03 2012-09-04 Western Digital (Fremont), Llc Double rie damascene process for nose length control

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4333227A (en) * 1979-11-29 1982-06-08 International Business Machines Corporation Process for fabricating a self-aligned micrometer bipolar transistor device
US4493740A (en) * 1981-06-01 1985-01-15 Matsushita Electric Industrial Company, Limited Method for formation of isolation oxide regions in semiconductor substrates
US4473598A (en) * 1982-06-30 1984-09-25 International Business Machines Corporation Method of filling trenches with silicon and structures

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61228650A (ja) * 1985-04-02 1986-10-11 Sony Corp 半導体装置の製造方法
JPS61229339A (ja) * 1985-04-04 1986-10-13 Fujitsu Ltd 半導体装置
JPS63186472A (ja) * 1987-01-28 1988-08-02 Mitsubishi Electric Corp 半導体集積回路装置およびその製造方法
JPH02158134A (ja) * 1988-12-12 1990-06-18 Sony Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
JPS6348180B2 (enExample) 1988-09-28
US4582565A (en) 1986-04-15

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