JPS6032344A - Package for semiconductor device - Google Patents

Package for semiconductor device

Info

Publication number
JPS6032344A
JPS6032344A JP58141577A JP14157783A JPS6032344A JP S6032344 A JPS6032344 A JP S6032344A JP 58141577 A JP58141577 A JP 58141577A JP 14157783 A JP14157783 A JP 14157783A JP S6032344 A JPS6032344 A JP S6032344A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
metal plate
plate
leads
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58141577A
Other languages
Japanese (ja)
Inventor
Nobuyuki Ikeda
信行 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP58141577A priority Critical patent/JPS6032344A/en
Publication of JPS6032344A publication Critical patent/JPS6032344A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

PURPOSE:To enable to use by brazing the back surface to a metal plate and to uniformly set the potential of a semiconductor substrate by arranging the metal plate integral with external leads for supplying a potential to a semiconductor substrate in a central recess of a ceramic base. CONSTITUTION:A metal plate 3 is buried and arranged in a central recess 2 of a base 1, and external leads 4 are removed by an integral metal from the plate 3. The plate 3 and the leads 4 are integrally press-molded together with other external lead group 5 by a leadframe machining technique. For example, a semiconductor substrate 6 is placed on the plate 3, electrodes on the same substrate 6 are connected via fine metal wirings 7 to the leads 4 and other external leads 5, and a ceramic sealing cover 8 is hermetically sealed by a low melting point glass material 9.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はセラミック封止半導体装置用パッケージに関す
るものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a package for a ceramic sealed semiconductor device.

従来例の構成とその問題点 従来、低融点ガラス材で封着する構造のセラミックパッ
ケージ、いわゆる、サーディツプ形パッケージでは、通
常、ＩＣチソグなどの半導体基板がセラミック基台部の
中央部凹所に塔載され、この半導体基板からの取シ出し
電極が前記セラミック基台部の平面上に配列された外部
リードの内端で金属細線接続される。ところで、半導体
基板を所定電位に設定したい場合、同半導体基板の表面
部に配設された接続用パンＬ′と外部リードの一端とを
金属細線で接続するが、径大な半導体基板では、同基板
電位を一様にするために、基板の裏面から、直接、電極
を取シ出す必要がある。Conventional configurations and their problems Conventionally, in ceramic packages sealed with a low-melting glass material, so-called cerdip packages, a semiconductor substrate such as an IC chip is usually placed in a recess in the center of a ceramic base. The electrodes taken out from the semiconductor substrate are connected with thin metal wires at the inner ends of external leads arranged on the plane of the ceramic base. By the way, when it is desired to set a semiconductor substrate to a predetermined potential, the connection pan L' provided on the surface of the semiconductor substrate is connected to one end of the external lead using a thin metal wire. In order to make the substrate potential uniform, it is necessary to take out the electrode directly from the back surface of the substrate.

発明の目的 本発明は、半導体基板の電位設定に好適なサーディツプ
形半導体装置用パッケージの構造を提供するものである
。OBJECTS OF THE INVENTION The present invention provides a structure of a cerdip type semiconductor device package suitable for setting the potential of a semiconductor substrate.

発明の構成 本発明は、要約するに、セラミック基台部の中央部凹所
に、半導体基板への電位供給用外部リードと一体の金属
板を配設した半導体装置用パッケージでちυ、これによ
り、半導体基板の裏面を前記金属板にろう付けして使用
でき、同半導体基板の電位を均等に設定することが可能
である。Summary of the Invention The present invention is a package for a semiconductor device in which a metal plate integrated with an external lead for supplying a potential to a semiconductor substrate is disposed in a central recess of a ceramic base. , the back side of the semiconductor substrate can be brazed to the metal plate, and the potential of the semiconductor substrate can be set uniformly.

実施例の説明 第１図は本発明実施例の概要図であシ、セラミツク基台
１の中央部に凹所２を有し、との凹所２内に金属板３を
埋め込んで配設し、この金属板３からは外部リード４が
一体金属によシ取シ畠されている。そして、前記金属板
３および前記外部リード４は、他の外部リード群５とと
もに、通常のリードフレーム加工技術によシ、一体的に
プレス成型される。DESCRIPTION OF EMBODIMENTS FIG. 1 is a schematic diagram of an embodiment of the present invention, in which a ceramic base 1 has a recess 2 in the center, and a metal plate 3 is embedded in the recess 2. From this metal plate 3, an external lead 4 is cut out of a single piece of metal. The metal plate 3 and the external lead 4 are integrally press-molded together with the other external lead group 5 by a normal lead frame processing technique.

第２図は、本発明実施例を用いて製作された半導体装置
の実体的断面図であり、半導体基板６を金属板３上に塔
載し、金属＃１線７によシ同半導体基板６上の各電極部
と、外部リード４および他の各外部リード５とを接続し
、セラミックの封止蓋８を低融点ガラス材９を用いて気
密封着したものである。なお、金属板３への半導体基板
６の接着には、なるべく低抵抗性のろう材を用いること
が好捷しいが、現実的には低融点はんだ材を介在させて
張シ合わせを行なえばよい。FIG. 2 is a substantial cross-sectional view of a semiconductor device manufactured using an embodiment of the present invention, in which a semiconductor substrate 6 is mounted on a metal plate 3, and a #1 metal wire 7 is connected to the semiconductor substrate 6. Each upper electrode portion is connected to the external lead 4 and each other external lead 5, and a ceramic sealing lid 8 is hermetically sealed using a low melting point glass material 9. Note that it is preferable to use a brazing material with as low resistance as possible to bond the semiconductor substrate 6 to the metal plate 3, but in reality, it is sufficient to use a low melting point solder material to perform the bonding. .

発明の効果 本発明によれば、セラミック基台部の中央部凹所に、半
導体基板への電位供給用外部リードと一体の金属板を配
設したので、同金属板上に半導体基板、たとえば、ＩＣ
チップをろう付けすることによシ、同半導体基板を確実
に所望電位に設定することができる。また、本発明によ
れば、通常の半導体接着技術（グイポンド）ならびに金
属細線接続技術（ワイヤボンド）が適用され、たとえば
従来のサーディツプ形パッケージで不可欠のセラミック
面へのメタライズ加工が不要になるなど、工程上の削減
も可能であシ、半導体装置の製造原価低減にも効用があ
る。Effects of the Invention According to the present invention, a metal plate integrated with an external lead for supplying potential to a semiconductor substrate is disposed in the central recess of the ceramic base, so that the semiconductor substrate, for example, can be placed on the metal plate. IC
By brazing the chip, the semiconductor substrate can be reliably set to a desired potential. Furthermore, according to the present invention, ordinary semiconductor adhesion technology (Guypond) and fine metal wire connection technology (Wirebond) are applied, which eliminates the need for metallization on the ceramic surface, which is essential in conventional cerdip packages. It is also possible to reduce process steps, and it is also effective in reducing manufacturing costs of semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明実施例の概要図、第２図は本発明実施例
による半導体装置の実体的断面図である。 １・・・・・・セラミック基台、２・・・・・凹所、３
・・・金属板、４，５・・・外部リード群、６・・・・
・・半導体基板、７・・・・金属細線、８・・・・・セ
ラミック封止蓋、９・・・・低融点ガラス利。FIG. 1 is a schematic diagram of an embodiment of the present invention, and FIG. 2 is a substantial sectional view of a semiconductor device according to an embodiment of the present invention. 1...Ceramic base, 2...Recess, 3
... Metal plate, 4, 5... External lead group, 6...
...Semiconductor substrate, 7.. Thin metal wire, 8.. Ceramic sealing lid, 9.. Low melting point glass.

Claims (2)

【特許請求の範囲】[Claims] （１）セラミック基台部の中央部凹所に、半導体基板へ
の電位供給用外部リードと一体の金属板を配設した半導
体装置用パンケージ。(1) A pancage for a semiconductor device in which a metal plate integrated with an external lead for supplying potential to a semiconductor substrate is disposed in a central recess of a ceramic base. （２）金属板および外部リードがセラミック基台面に密
着固定された特許請求の範囲第１項に記載の半導体装置
用パッケージ。(2) The package for a semiconductor device according to claim 1, wherein the metal plate and the external leads are closely fixed to the ceramic base surface.
JP58141577A 1983-08-02 1983-08-02 Package for semiconductor device Pending JPS6032344A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58141577A JPS6032344A (en) 1983-08-02 1983-08-02 Package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58141577A JPS6032344A (en) 1983-08-02 1983-08-02 Package for semiconductor device

Publications (1)

Publication Number Publication Date
JPS6032344A true JPS6032344A (en) 1985-02-19

Family

ID=15295216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58141577A Pending JPS6032344A (en) 1983-08-02 1983-08-02 Package for semiconductor device

Country Status (1)

Country Link
JP (1) JPS6032344A (en)

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