JPS60217641A - 集積回路装置 - Google Patents

集積回路装置

Info

Publication number
JPS60217641A
JPS60217641A JP7381384A JP7381384A JPS60217641A JP S60217641 A JPS60217641 A JP S60217641A JP 7381384 A JP7381384 A JP 7381384A JP 7381384 A JP7381384 A JP 7381384A JP S60217641 A JPS60217641 A JP S60217641A
Authority
JP
Japan
Prior art keywords
substrate
chip
integrated circuit
cover
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7381384A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0357619B2 (enrdf_load_stackoverflow
Inventor
Yuji Iwata
岩田　勇治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7381384A priority Critical patent/JPS60217641A/ja
Publication of JPS60217641A publication Critical patent/JPS60217641A/ja
Publication of JPH0357619B2 publication Critical patent/JPH0357619B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP7381384A 1984-04-12 1984-04-12 集積回路装置 Granted JPS60217641A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7381384A JPS60217641A (ja) 1984-04-12 1984-04-12 集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7381384A JPS60217641A (ja) 1984-04-12 1984-04-12 集積回路装置

Publications (2)

Publication Number Publication Date
JPS60217641A true JPS60217641A (ja) 1985-10-31
JPH0357619B2 JPH0357619B2 (enrdf_load_stackoverflow) 1991-09-02

Family

ID=13528968

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7381384A Granted JPS60217641A (ja) 1984-04-12 1984-04-12 集積回路装置

Country Status (1)

Country Link
JP (1) JPS60217641A (enrdf_load_stackoverflow)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5379191A (en) * 1991-02-26 1995-01-03 Microelectronics And Computer Technology Corporation Compact adapter package providing peripheral to area translation for an integrated circuit chip
US5682061A (en) * 1990-09-24 1997-10-28 Tessera, Inc. Component for connecting a semiconductor chip to a substrate
US5685885A (en) * 1990-09-24 1997-11-11 Tessera, Inc. Wafer-scale techniques for fabrication of semiconductor chip assemblies
US7098078B2 (en) 1990-09-24 2006-08-29 Tessera, Inc. Microelectronic component and assembly having leads with offset portions

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5682061A (en) * 1990-09-24 1997-10-28 Tessera, Inc. Component for connecting a semiconductor chip to a substrate
US5685885A (en) * 1990-09-24 1997-11-11 Tessera, Inc. Wafer-scale techniques for fabrication of semiconductor chip assemblies
US5848467A (en) * 1990-09-24 1998-12-15 Tessera, Inc. Methods of making semiconductor chip assemblies
US7098078B2 (en) 1990-09-24 2006-08-29 Tessera, Inc. Microelectronic component and assembly having leads with offset portions
US7198969B1 (en) 1990-09-24 2007-04-03 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US7271481B2 (en) 1990-09-24 2007-09-18 Tessera, Inc. Microelectronic component and assembly having leads with offset portions
US7291910B2 (en) 1990-09-24 2007-11-06 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5379191A (en) * 1991-02-26 1995-01-03 Microelectronics And Computer Technology Corporation Compact adapter package providing peripheral to area translation for an integrated circuit chip

Also Published As

Publication number Publication date
JPH0357619B2 (enrdf_load_stackoverflow) 1991-09-02

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