JPS60214050A - Detecting circuit for microcomputer runaway - Google Patents

Abstract

PURPOSE:To prevent securely an accident resulting from a runaway by detecting the period abnormality of a basic clock on the basis of the counted value of a counter which operates on the basis of a basic clock and an abnormality detection timing signal. CONSTITUTION:The basic clock is supplied from a microcomputer 1 to a control signal generating circuit 3, which detects the positive and negative leading and trailing edges of the basic clock to generate a counter reset signal corresponding to the leading edge, and a gate signal, abnormality detection timing signal, and counter enable signal corresponding to the trailing edge. Those signals are supplied to a counter 8 and an abnormality amplitude detecting circuit 5, which detects the period abnormality of the basic clock on the basis of the counted value of the counter 8.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microcomputer runaway detection circuit that detects abnormalities in long and short cycles of a basic clock oscillated by a microcomputer, thereby detecting runaway of the microcomputer.

In order to detect runaway in a microcomputer and promptly recover it, it is necessary to monitor the cycle of the basic clock oscillated by the microcomputer and detect whether it is always within the correct range.

For this purpose, there is a circuit called a watchdog timer as a basic clock cycle abnormality detection circuit conventionally used.

This charges a capacitor using the basic clock as the object to be inspected, and monitors the potential across it.While the basic clock is outputting normally, the potential across the capacitor also remains within a certain range, but the basic clock When the period of the basic clock becomes abnormally long, the potential across the capacitor drops below a threshold value, which is used to detect an abnormality in the period of the basic clock.

However, conventional runaway detection circuits or basic clock cycle abnormality detection circuits based on this principle have the drawback that they cannot detect when the basic clock cycle becomes abnormally short, that is, short cycle abnormalities. Ta.

The present invention has been made in view of this point, and is intended to be used when the basic clock period oscillated by a microcomputer becomes abnormally long beyond the permissible period (or indirectly, pulse width) range that can be considered as normal operating condition. In addition, it is an object of the present invention to provide a microcomputer runaway detection circuit that can detect abnormally shortened lengths as well.

The structure, operation, and effects of the present invention will be explained below through embodiments of the present invention shown in the accompanying drawings. First, FIG. 1 shows a principle or basic embodiment of the microcomputer runaway detection circuit of the present invention. It shows.

The object to be tested is the basic clock CP oscillated by the microcomputer 1. This basic clock CP is obtained by appropriately dividing the master clock PO oscillated by the external oscillator 2 attached to the microcomputer 1, and is not properly programmed. is executed, the pulse train generally has a duty of 50%.

Therefore, when the basic clock CP is logically at the "H" level or the "L'" level, its pulse width is the same TO. In this embodiment, this pulse width or half period TO is monitored.

In the present invention, such basic clock CP is first given to the control signal generation circuit 3. This control signal generation circuit 3
detects the rising edge and falling edge of the basic clock CP in the positive or negative direction, and detects the counter reset signal Sr corresponding to the rising edge and the gate signal or abnormality corresponding to the falling edge. When neither of these signals Sr and Sg is generated, or at least over time, the detection timing signal Sg is generated after the counter reset signal Sr is generated. Until this happens, a counter enable signal Se is generated.

Both the counter reset signal Sr and the counter enable signal Se are applied to the counter 8, and when the counter 8 receives the counter enable signal Se, the counter 8 counts the master clock PO and sequentially outputs the result as the count output Sc. Of course, the counter reset signal S
When r is given, the count content Sc is reset to zero.

The abnormal oscillation detection circuit 5 constantly monitors the count output Sc of the counter 8 and outputs a counter enable signal Se.
After the generation of , check whether the time when the master clock Po reaches a predetermined numerical range coincides with the generation time of the detection timing signal Sg, or whether this count output is within a predetermined numerical range set by hardware. It is determined whether Sc is present or not.

Therefore, the detection timing signal s from the control signal generation circuit 3
If the count output Sc of the abnormal oscillation detection circuit 5 is outside the predetermined range when g is given, or if the time point at which the predetermined numerical range is counted is out of line with the generation timing of the detection timing signal Sg, then This is the result of either a long or short cycle abnormality occurring in the basic clock CP, and the abnormality detection signal So from the abnormal oscillation detection circuit 5.
is output.

Although the present invention does not directly specify how this abnormality detection signal So is to be used, a commonly considered use is to use it as a reset signal for the microcomputer I. Basic clock C
This is because when some abnormality occurs in P, it is safest to return the microcomputer l to its initial state.

FIGS. 2 and 3 show a slightly more specific embodiment constructed in accordance with the principle embodiment shown in FIG. 1, and waveform diagrams of various parts thereof.

The microcomputer 1 as an oscillator of the basic clock CP to be tested in FIG. 2 is in an operable state when the reset power is raised to the power supply potential or logic "H", and is approximately at ground potential or logic "H". When it is pulled down to L', it is set at least once.In other words, the microcomputer reset signal SO is significant at logic "L".However, of course, this is not limited to,
The form of the microcomputer reset signal SO may be matched to the reset mode of the target microcomputer. Further, in this embodiment, a binary counter with an enable input is used as the counter 8, but its capacity and output pill may be appropriately selected so as to satisfy the following explanation.

The basic clock CP from the microcomputer 1 is inverted via an inverter 31 in the control signal generating circuit 3 and then applied to the integrating circuit 32. Therefore, the signal waveform at point 0 in FIG. 2 is as shown in the third row of FIG. It becomes dull according to a constant. This is shown as an approximation.

First, the counter reset signal Sr is generated by ANDing the 0 point signal and the basic clock CP using an AND gate 33. That is, the Ant Gate 3
High and low transition thresholds, resistance R and capacitor C at the input of 3
If the time constant is determined appropriately, as shown at point 0 in Fig. 3, the counter resets to logic "H" for a predetermined period of time α from the rising edge of each period of the basic clock CP in the positive direction. A signal Sr is obtained.Therefore, the counter 8 is once reset with each positive rise of each period of the basic clock CP.

On the other hand, similarly in the positive direction, at each falling edge of each period of the basic clock CP, a gate signal or a detection timing signal S'g to the abnormal oscillation detection circuit 5 is generated. In other words, the 0 point signal and the basic clock CP are connected to the NOR gate 34.
Therefore, as shown in point ■ in Figure 3,
A detection timing signal Sg whose pulse width β is determined is generated depending on the high/low transition threshold at the input of the shear gate 34 and the time constant of the integrating circuit 32. Conversely, in the case of this embodiment, each falling point of the basic clock CP for one shot is selected as the timing for outputting the abnormality detection result from the abnormal oscillation detection circuit 5, which will be described later. The threshold values of the AND gate 33 and the NOR gate 34 described above are schematically shown in FIG. 3 as broken lines across the transition period of the integral waveform.

The counter enable signal Se is generated by taking the NOR gate 35 between the counter reset signal Sr and the detection timing signal Sg.

Therefore, in this embodiment, the counter enable signal Se becomes a significant level "H" when both the counter reset signal Sr and the detection timing signal Sg are not at a significant logic level, that is, when they are at a logic "L'". This is shown at point 0 in FIG.

The counter 8 counts the master clock PO when a significant counter enable signal Se is given at logic "H"', and the count output Sc is manually inputted to the delay time setting circuit 51 in the abnormal oscillation detection circuit 5. , The output signal waveform of the delay time setting circuit 51 indicated by the point ■ in FIG. 2 is shown in the third row from the bottom in FIG. It is defined as a pulse waveform that falls to a logic "L" degree over a permissible time range γ in which the cycle of is considered normal.

As can be seen from the above-mentioned time relationships, the following time relationships are satisfied when the basic clock CP oscillates within a normal cycle range. However, the pulse width β of the detection timing signal Sg described above is set to be smaller than the pulse width γ of the point signal.

TI+(X≦To≦71+α+7 ,,,,,,,■
βkuγ 6600011. ■ The output of the delay time setting circuit 51 is the detection timing signal Sg.
The AND gate 52 performs an AND operation. Therefore, if the output of the delay time setting circuit 51 is logic ``H'' at the detection timing, it indicates that some abnormality has occurred in the basic clock CP. , logic "L''' indicates that there is no abnormality. This point will be explained in more detail.

As shown in the "normal °' range in FIG. 3, as long as the basic clock CP satisfies the above equation 0, as is clear from FIG. 3, when the detection timing signal Sg is issued, there is a delay time. The signal waveform of the 0 point as the output of the setting circuit 51 is always at logic "L", so even if the detection timing signal Sg indicating that it is the detection timing is applied to the AND gate 52 alone, the output of the AND gate 52 is Output (0
point) maintains the previous logic "L", and the abnormality detection signal or microcomputer reset signal So via the inverter 53 also maintains the non-significant logic "H". That is, the microcomputer 1 can continue to operate without being reset.

However, for example, a disturbance occurs in the period of the basic clock CP, and one of the conditions in the above equation 0 goes out of order, resulting in To<Tl+α 0090016. ■ If this happens, the detection timing signal Sg, which indicates the fall of the basic clock CP as the detection timing, rises to logic "H'" at point ■, as shown in the "short cycle abnormality" range in Figure 3. At this time, since the predetermined time Tl has not elapsed since the fall of the counter reset signal Sr, the 0 point output of the delay time setting circuit 51 is still at the logic "H" degree at the point ■ which is the same time as the point ■. occurs.

Then, since both of the re-inputs of the AND gate 52 become logic "H", the output of the AND gate 52 becomes H°' as shown by point (■), and the abnormality detection signal or microcomputer reset signal is output via the inverter 53. So is a dot■
The signal becomes significant level "L"' and the microcomputer 1 is reset as expected.

Next, the basic clock period becomes longer than the specified range °“
The long period abnormality will be explained.

Another condition of the 0 formula mentioned above is impaired, and To>TI+
Assuming that α+γ ・・・・・・・・・■, as shown in the ``Long period abnormality'' range in Figure 3, even if the detection timing signal Sg is generated at time ■, it is already too late and the delay time The boiling output signal of the setting circuit 51 has already reached the predetermined time α+T1.
Since +γ has passed, a state occurs in which the signal returns from "L'" to "H" (point ■).

Then, at this point, similar to the previous short cycle abnormality,
As shown by the dot (■), the AND gate 52 performs an AND operation, and therefore, a significant abnormality detection signal So at logic "L" is output, and the microcomputer 1 is reset.

In the above explanation, the delay time setting circuit 51 is shown as a black box, but this is because those skilled in the art can construct various configurations to satisfy the functions required of the delay time setting circuit 51. This is because the present invention does not directly define this.

For example, the counter 8 that counts the mask clock PO
An appropriate gate array may be constructed for each focus output port of the counter 8 so that logic "L" is obtained at the gate circuit output of the final stage when the counter is counting a predetermined numerical range set in advance. Among the counter output ports, the inversion of the output port that inverts the output after T1 time has elapsed after the input of the counter reset signal Sr activates the monostable multivibrator connected to it, and as its output. It is also possible to obtain a pulse over a predetermined time γ.Of course, various other configurations are possible as described above.

Furthermore, in the above logic operation, the conversion between positive logic and negative logic is of course within the obvious range. For example, the counter reset signal Sr is obtained at the rising edge of the basic clock CP in the negative direction, and the counter reset signal Sr is obtained at the falling edge of the basic clock CP in the negative direction. The detection timing signal Sg may be obtained (that is, at the transition from logic "L'° to "H"').

In any case, as explained above, according to the present invention, even if a program goes out of control due to unexpected external noise, etc., this can be reliably detected in both cases where the basic clock exceeds the period range above and below the normal state. Since the microcomputer can be quickly reset if necessary, serious accidents due to runaway can be avoided.

Claims (1)

[Scope of Claims] A microcomputer runaway detection circuit that detects a cycle abnormality in a basic clock from a microcomputer obtained by dividing a mask clock oscillated by an oscillator, and detects runaway of the microcomputer; ” 1. According to the rising and falling of the basic clock,
a control signal generation circuit that generates a counter reset signal and an abnormality detection timing signal, respectively, and generates a counter enable signal at least after the generation of the counter reset signal until the abnormality detection timing signal described in 1. a counter that is controlled by the counter reset signal and the counter enable signal and counts the master clock in accordance with the counter enable signal; detects a cycle abnormality of the basic clock based on the count output of the counter; A microcomputer runaway detection circuit comprising: an abnormal oscillation detection circuit that outputs the detection result based on a timing signal; and a microcomputer runaway detection circuit.