JPS63305436A - Output control device for microcomputer - Google Patents

Abstract

PURPOSE:To surely inhibit load driving at the time of generating abnormality in a microcomputer by inputting a reset signal to the microcomputer at a prescribed period when a watchdog signal is interrupted for a prescribed time, and after releasing a reset state, inhibiting the output of the microcomputer during the period of the reset signal or more. CONSTITUTION:When the watchdog signal C is interrupted for the prescribed time, a load drive inhibiting means inhibits the load driving of the microcomputer 11 during the period of the reset signal or more. The reset signal is generated when the signal C is interrupted and its period is more than the main routine processing time of a normal program. Consequently, the generation of load driving due to an abnormal output from the microcomputer 11 can be prevented by inhibiting the load driving over one period or more of the reset signal after releasing the reset signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output control device for a microcomputer.

[Conventional technology]

FIG. 3 shows a conventional microcomputer output control device. In the figure, ■, 2 is a comparator, R1, 3 ~
5, 7-8 are resistors s C1 is a cone capacitor.

6 is a Zener diode, which constitutes an initial reset pulse generation circuit. 9 is or c-), 10
62 (mpata, 11@-j microcomputer, 1
2 and 13 are AND gates, 14.15 is a load, 16 is a rising differential circuit, 17 is a falling differential circuit, 18.19 is an OR gate, Trr is a transistor, R1 is a resistor s C2
20 is a capacitor, 21 to 24 are resistors, 25 is a diode, a 26-wire inverter, and 27 is a free-lag frog.

Next, the operation of the above configuration will be explained using the time chart of FIG. 4. First, when the power is turned on, the input of the converter 1 becomes equal to or higher than the Zener voltage VZ.

Output of comparator 1 VC1 from L (low level) to H
(High level health) Due to charging of capacitor cl, the voltage rises with a time constant of τ''CIR+.When vcl becomes equal to or higher than the reference voltage VT of comparator 2, the output A of the comparator 2 changes from H to L, and OR r - The reset signal changes from L to H via the gate 9 and the inverter 10t, and the microcomputer 11 is released from reset, starts operation, and ends the initial reset period.

10,000, the output of microcomputer 11 Itako P.

is a watchdog signal C that repeats H and Lt-< at predetermined intervals.
is output after the reset is released, and the signal C repeats on and off. Signal C is connected to each differentiator circuit 16, 17 and orto 1
It becomes a signal via 8. Signals A and D are or dirt 19
The signal F becomes the signal F through the transistor Trl.
is input. When signal F becomes H, Trl becomes conductive and capacitor C3 is discharged. For other periods, capacitor C
1 is photoelectronized with a time constant τ-value CtRt, and the voltage VC2 has a sawtooth shape as shown. When the output M of the filtration generator 20 becomes H when the power is turned on, the 10 input of the condenser 20 also becomes H (
1! During normal operation of the microcomputer 11, VC2 never reaches VQ, and the output M becomes H.

Here, when the watchdog signal C is interrupted, the signal is also interrupted, the voltage VC2 reaches VQ, and the output M changes from H to L. This instantaneous reset signal also becomes H, and the microcomputer 11 is reset. When the output M becomes L, the capacitor C! is discharged and VC2 becomes less than VG,
The output M becomes H again and the reset signal also becomes H. This operation is repeated at all predetermined cycles. Free Lug Frog 2
A signal is input to the reset input of 7, and when the signal becomes H, the page output becomes H, and the AND c-to 12, 13'r
The output of the output electrons Pa, R is supplied to a load 14.15 via. Also, when the output M becomes LVC due to the stop of the watchdog signal C, the Q output t of the free lag frog 27
2L, terminal P. , P, is no longer supplied to the load.

[Problem that the invention seeks to solve]

However, in the conventional device described above, when the watchdog signal C is interrupted during operation, it is immediately reset, and after this reset is released, load driving is immediately permitted when the watchdog signal C is restored. 11 abnormal modes cannot be reliably prohibited.

The problem of incorrect output control was frequently encountered.

That is, as shown in FIGS. 5 and 6, the watchdog signal C repeats on and off every 5 ms with a period of 10 m.
5) If the main program processing time is up to 30m5, if a memory error occurs 20m5 after starting at the final step 100, the watchdog signal C will be output until the final step 100 is reached, and an error will occur in the microcomputer 1. Even though this occurred, load driving was performed. This is explained by Ts and Ty in Figure 4.
It is also shown in the period.

This invention was made to solve the above-mentioned problems, and an object thereof is to provide an output control device for a microcomputer that can reliably prohibit load driving when an abnormality occurs in the microcomputer. shall be.

[Means for solving problems]

The output control device for a microcomputer according to the present invention includes a reset means for inputting a reset signal to the microcomputer at a predetermined period when a watchdog signal is interrupted for a predetermined period of time, and a reset means for inputting a reset signal to the microcomputer at a predetermined period after the reset is released, A load drive prohibition means is provided to prohibit the output of the output.

[Operation] The load driving prohibition means according to the present invention prohibits the microcomputer from driving the load for at least a period longer than the period of the reset signal after the reset is released when the watchdog signal is interrupted for a predetermined period of time. The reset signal is generated when the watchdog signal is interrupted, and its cycle is usually longer than the main routine processing time of the program. Therefore, if load driving is prohibited for one period or more after the reset signal s is removed (if the watchdog signal stops, a reset signal is generated and the load driving time restarts).
, load driving due to abnormal output of the microcomputer is prevented.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. 1st
The figure shows the configuration of a microcomputer output control device according to the present invention, where Rs and R4 are resistors.

Trz is a transistor, 28 is an inverter, Rs, 29
31 is a resistor, Trs is a transistor, C, ra capacitor, 32 is a condenser, and 33 is an ANDr-). The other configurations are the same as in FIG. 3.

Next, the operation of the above configuration will be explained using the timing chart of FIG. 2. The reset signal becomes HK in response to the fall of the signal A, the reset is released, and the watchdog signal C is output after a short period of time. Annoyed by this, I signaled,
F is output and the conde photoelectric is repeated h VG2 is vG
The output M becomes HK because it does not reach . For this reason, Tr
Since s is off and lower than Vcsh Vx, the output J of the connector 32 becomes H, and the output EE (H level) reaches the AND gates 12 and 13 via the AND gate 33 (output K), and the micro The output of the computer If is supplied to the load. Also, since the output J is H, Trz
turns on and resistors & and Rs are connected in parallel, resulting in the time constant as described above.

Here, if a log error occurs in the microcomputer 11 and the watchdog signal is interrupted, the TRX remains off and the capacitor Ct is not discharged, so the VG2
becomes larger than VG, and the output M becomes L. For this reason,
The output E becomes L, and the reset function is performed and sVG2 decreases. When Trs is turned on, the capacitor C8 is photoelectronized and VCS rises, the output J also becomes L, and Trz is turned off. Therefore, no output is supplied to the load.

As vG2 decreases, the output M immediately returns to H, and the reset is released.

Does capacitor C2 have a time constant Ctf? - photoelectrically b
When VG2 reaches vG, the output M becomes L and the above operation returns <9. On the other hand, even if the output M becomes H, the capacitor c1
Since the discharge of is slow, the output J remains at L. When the watchdog signal returns after the reset is released, output E also returns to H, but output J remains at L.

No load driving is performed. And watchdog signal C
When VG3 is continuously output a predetermined number of times, the output J becomes H due to a decrease in VG3, and load driving is performed.

Therefore, the load drive prohibition time is determined by the discharge time constant CsR5 of the capacitor C3, but this time may be set to at least one cycle of the reset signal. That is, the reset signal is output when the watchdog signal C is interrupted, and its period is normal! Since the time is longer than the main flow processing time of the program, it is sufficient to stop the output for this period (if the watchdog signal C is stopped during this period, a reset signal will be generated and the load drive prohibition time will start from zero again. ).

Note that the output K is kept at L to prohibit load driving even after the initial reset is released until the watchdog signal is output.

〔Effect of the invention〕

As described above, according to the present invention, when a reset signal is generated at a predetermined period due to interruption of the watchdog signal, load driving is prohibited for a predetermined period of time even if the watchdog signal is generated.

Even if an abnormality occurs in the final part of the program, the load will not be driven by the abnormal output of the microcomputer, allowing accurate output control. Further, the reset means and the load drive prohibition means can be configured by a timer, and the configuration is simple.

[Brief explanation of drawings]

1 and 2 are a circuit diagram and a timing chart of this invention device, respectively, FIGS. 3 and 4 are a circuit diagram and a timing chart of a conventional device, respectively, and FIGS. 5 and 6 are
The figures are a schematic main flowchart and a corresponding timing chart of a conventional device, respectively. 1.2, 20.32... Kontsu Crater, C1-C3
...Capacitor, 9.19...Or gate, 11.
...Microcomputer, 12, 13.33...And dirt, 14,15...Load, Tr1 to Trs.
...Transistor. Note that the same reference numerals in Figure 1 indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a microcomputer that outputs a watchdog signal that alternately changes to high and low levels at predetermined intervals while the program is operating normally after reset release,
Resetting means for inputting an initial reset signal to the microcomputer when the power is turned on, and determining that the program has runaway when the watchdog signal is interrupted for a predetermined period, and inputting a reset signal to the microcomputer at a predetermined period;
The microcomputer's load drive output is prohibited until the watchdog signal is generated after the initial reset is released, and if the watchdog signal is interrupted for a predetermined period of time, the microcomputer's load drive output is prohibited for at least the period of the reset signal after the reset is released. 1. An output control device for a microcomputer, characterized in that it is equipped with load drive prohibition means for prohibiting load drive.