JPS61165143A - Malfunction preventing system of cpu - Google Patents

Abstract

PURPOSE:To decide whether a CPU is normal or abnormal, and to initialize or stop the CPU by counting for a prescribed time a clock pulse outputted from the CPU, and comparing it with a normal count value which has been prescribed in advance. CONSTITUTION:An oscillator 1 gives a reference clock pulse CL to a CPU3. This clock pulse CL is inputted to a counter 4, and the counter 4 which has been reset by a resetting circuit 6 at a rise of a reference pulse T0 given by an oscillating circuit 2 counts the clock pulse CL in a period of until a rise of the reference pulse T0. The count number N is sent to a deciding circuit 5, and in case of N1-N2, and other case, they are regarded as normal and abnormal, respectively, and an external notice is issued, and the CPU itself is reset as necessary.

Description

DETAILED DESCRIPTION OF THE INVENTION (7') Technical field This invention is based on CPU (Cantral Process
This invention relates to a method for preventing malfunction of the sing Unit.

The CPU operates by receiving clock pulses from a certain oscillator. Efforts are being made to stabilize the frequency of the clock pulse by using a crystal oscillator. However, the frequency is not necessarily stable. Also C
The PU operates over a wide frequency range (e.g. l MHz
~3M)IZ) Therefore, even if the frequency of the oscillator fluctuates, it operates as usual.

Therefore, it is not possible to detect frequency bias from the CPU.

However, variations in the pulse frequency of the clock pulses may cause malfunctions in circuits and elements other than the CPU. Therefore, it may be necessary to monitor abnormalities in the clock pulse frequency.

(B) Prior art There is no prior art that monitors the speed of the clock pulse of the CPU. At least the inventor does not know.

(1) Purpose The purpose of the present invention is to learn a circuit that diagnoses whether the clock pulse speed of a CPU is normal or abnormal.

2) Configuration FIG. 1 shows a block diagram of the malfunction prevention system of CPt1 of the present invention.

The oscillator 1 can learn the reference clock pulse CL from the CPU 3. The CPU 3 is connected to various external circuit elements, memories, etc., but these are not shown. The purpose of using the CPU and the functions of the circuit elements surrounding the CPU are arbitrary. The present invention can be applied to any purpose, and the presence of any circuit elements does not impede the implementation of the present invention.

In the present invention, an oscillation circuit 2 is newly provided as a reference for time measurement. The oscillation circuit 2 uses a crystal oscillator to strictly define the frequency. It takes a fairly long time T, including a suitable frequency divider. It is designed to generate a pulse whose period is □. Then, set the duty to 50% and To/
2 becomes L and To/2 becomes H. Although the duty is arbitrary, the explanation will be made by setting it to 50%.

When) Y U CPU Let t be the period of the clock pulse issued by U. To is a long time many times t.

A new counter 4 will also be installed. The clock pulse CL outputted from the CPU to the outside is inputted to the clock input Ck. This counter 4 counts the number of clock pulses CL. There is no problem whether you count the rising edge of the pulse or the falling edge of the pulse.

The output of the oscillation circuit 2 is connected to the enable terminal E of the counter 4. When the output of the oscillation circuit 2 is H, the counter 4
counts, and when the output is L, the counter 4 stops counting.

Reference pulse T. At the rising edge of , the counter 4 is reset. For this reason, the reference pulse To is input into the reset circuit 6 to make it into a short pulse, and this is input to the reset terminal H of the counter 4. The reset circuit 6 may be like a one-shot multivibrator that produces short pulses.

At the rising edge of the reference pulse To, the one-shot multivibrator is triggered and produces a short pulse (pulse width τ), which resets the counter 4. The width τ of the reset 1 pulse must be significantly shorter than the clock pulse.

Reference pulse T. Since the counter 4 is reset at the rising edge of , the counter value becomes O. At the same time, the enable terminal E becomes 1, so the counter 4 starts counting the number of clock pulses CL.

After T O/2, the reference pulse falls and the enable terminal becomes L. Therefore, the counter stops counting. Assume that the count value is N.

The period during which the counter was counting is T. /2, the number of clock pulses N should be approximately equal to To/2t.

The judgment circuit 5 has N and T. /2t. If the value of N is close to this value, there is no deviation in the period of the clock pulse CL.

On the other hand, the value of N is T. /2t, this is the reference pulse T. Or, the frequency of the clock pulse CL is fluctuating.

To make it easier, predetermine values N1 and N2 close to To/2t, and calculate N1, N S N, (
11〈, it is determined that the frequency is normal; otherwise, it is determined that the frequency of the clock pulse is abnormal.

A signal indicating normality or abnormality is emitted from the judgment circuit 5 to the outside. The abnormal signal has the meaning of a warning and a correction signal.

A warning is used to notify the operator that the CPU clock pulse is abnormal and to make the operator aware of the need for inspection and repair.

Some broken external circuits may malfunction due to fluctuations in the CPU clock frequency. However, if the variation in clock frequency is known, the operation of the external circuitry can be modified to match this. It can also be used as a correction signal for this purpose.

The broken abnormal signal is input not only to the external circuit but also to the CPU 3. The CPU may also be reset.

Furthermore, in addition to being provided separately, the determination circuit 5 is provided by the CPU 3
It may also be done by itself.

Note that the reference pulse need not have a duty of 50%, of course.

To=='r, +T,, (
As 2), the counting operation may be performed for the period T, and the counting may be stopped for the period T20. Also, instead of resetting at the rising edge, it is also possible to issue a reset pulse during the count stop period T2.

In this case, there is no problem even if the pulse width generated by the reset circuit 6 is somewhat long.

(B) Effect Detects frequency abnormalities in the clock pulses input to the CPU, diagnoses CPU abnormalities, and prevents malfunctions of the CPU and external circuits controlled by the CPU.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a CPU malfunction prevention system according to the present invention. 1... Oscillator 2... Oscillation circuit 3... CPU 4... Counter 5...
・Judgment circuit

Claims (1)

[Claims] Outputs the clock pulses output from the CPU, counts the number of clock pulses for a certain period of time T_1, compares the counted value with a predetermined normal count value, and determines whether the clock pulses are normal or abnormal. A CPU malfunction prevention method characterized by determining whether the CPU is normal or abnormal and initializing the CPU or stopping its operation in the event of an abnormality.