JPS6111858A - Abnormality detector - Google Patents

Abstract

PURPOSE:To constitute simply the titled device only of hardware by deciding the loss of the periodical change of a control signal level outputted from a CPU on the basis of logic to detect abnormality. CONSTITUTION:At the normal operation of the CPU1, a constant of a pulse generating circuit 12 is set up so that a logic circuit 11 generates a retrigger signal at a certain period fixed by the combination of two control signal periods in a pulse generating period and the output of an inverter 16 is always kept at the ''0'' level. At that time, the coil 17 of a relay is out energized and a contact 18 is not closed, so that no alarm is generated. When the CPU 11 is failed and a control signal is lost, the pulse generating circuit 12 stops pulse generation, so that the output of the inverter 16 is turned to the ''1'' level, the relay coil 17 is energized, the contact 18 is closed, and the alarm device 8 is actuated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a digital control device incorporating a central information processing unit (hereinafter referred to as a CPU), and particularly to an abnormality detection device for the CPU.

[Prior art]

A watch dog timer (hereinafter referred to as WDT) having a configuration shown in FIG. 1 has conventionally been used as a device for detecting abnormalities in the CPU of this type of digital control device. In the same figure,
1 is a CPU, 2 is a memory containing programs and data, 3 is a data bus, 4 is a data output buffer, 5 is an abnormality detection device, 6 is a clock generation circuit, 7 is a preset counter, and 8 is an alarm.

In this configuration, while the CPUI is operating normally, the predetermined time intervals TNI, TN
2. Preset values N1, N2, N3 for each TN3...
... is programmed to be set in the preset counter, and this preset value is counted down in synchronization with clock C, but as long as each of the above preset values continues to be set at each predetermined time interval, the preset value is The contents of the counter 7 will never become 0, and the alarm device 8 such as a lamp will not issue an alarm. However, the CPU
1 and the preset value is no longer set, the contents of the preset counter 7 count down to 0, and the alarm device 8 issues an alarm.

In this conventional device, in order to set the preset value in the brisset carantuff, as shown in FIG. Since it is necessary to create a program, and the data bus 3, data output buffer 4, and wiring for these are used, both the software and the hardware become complicated.

[Summary of the invention]

The present invention has been made in order to eliminate the above-mentioned conventional drawbacks, and it extracts a control signal whose level changes at a constant period from among the control signals sent out by the CPU, and determines whether or not the level change of the control signal is lost. By determining whether there is an abnormality in the CPU or not, the present invention proposes an abnormality detection device that does not require a program for abnormality detection as in the past and requires only a simple hardware configuration.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

Ru.

In FIG. 5, reference numeral 10 denotes a determination circuit that receives one or more control signals whose level changes at a certain period among the control signals output by the CPU, and determines whether these control signals have changed within a certain period. If there is no change, the alarm circuit drive signal is sent to the alarm circuit 20.
.

FIG. 5 shows a specific example of the determination circuit 10 and the alarm circuit 20. In the determination circuit 10, logic circuits 11 and 12 are composed of pulse generation circuits. This logic circuit 11 is, for example, an AND circuit, and receives a plurality of the above control signals from the CPUI, and sends out a re-trigger signal r to the pulse generation circuit 12 when both of these control signals are generated.

The pulse generating circuit 12 outputs a pulse P determined by the resistance value of the resistor 13 and the capacitance value of the capacitor 14.

15 is a power supply, 16 is an inverter, 17 is a coil of an alarm relay, 18 is a contact of the alarm relay, and 19 is a diode.

In this configuration, the constant of the pulse generation circuit 12 is set so that the logic circuit 11 generates the re-trigger signal T during the generation period of the pulse P with a certain period determined by the combination of the above two control signal periods when the CPUI is in normal operation. is set. When this retrigger signal γ is generated within the pulse generation period of the pulse generation circuit 12, the pulse generation circuit 12 is retriggered, so that the duration of the pulse P that it outputs is extended, and the inverter 16 The output is always at the θ level, the relay coil 17 is not energized, and the contact 18
Since the circuit does not close, no alarm is generated. , but CF'
If the UI fails and the control signal is lost, the pulse generation circuit 1
2 stops sending out the pulse P, the output of the impark 16 becomes a level, and the coil 17 of the relay is energized, so the contact 18 is closed and the alarm 8 is activated by the contact output.

In the above embodiment, a case has been described in which an abnormality in a CPU is detected, but it is clear that the present invention can also be used to detect a failure in a peripheral device of a CPU.

In the above embodiment, the alarm circuit 20 is configured to generate a contact signal as an alarm signal.
It is also possible to use the logic signal as an alarm signal, and this alarm signal can be used as an interrupt signal for CPU error processing, as well as as a CF'UI reset signal, power stop signal, etc. You may use it.

〔Effect of the invention〕

As described above, the present invention has the advantage that it can be easily configured using only hardware because it uses logic to determine the loss of periodic changes in the level of the control signal output by the CPU to detect an abnormality.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional abnormality detection device, FIG. 2 is an explanatory diagram of the operation of the conventional device, FIG. 3 is a flowchart of the program of the conventional device, and FIG. 4 shows an embodiment of the present invention. The block diagram, FIG. 5, is a specific circuit diagram of the above embodiment. In the figure, 8-alarm device, 10--judgment circuit, 11-
・・Logic circuit, 12-pulse generation circuit, 20-・-
Alarm circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Figure 1 7a, 7C1, 1111111111, 1111111
111111111Figure 3Figure 4Figure 5 - Touch 1

Claims (1)

[Claims] One or more control signals whose level changes at a constant period among the control signals outputted by the central information processing unit are provided, and a determination circuit is provided to detect loss of the level change, and when the level change of the determination circuit is lost, An abnormality detection device characterized in that an alarm is driven by the output of.