JPS60100235A - Self-diagnosing circuit - Google Patents

Abstract

PURPOSE:To detect the abnormality of a system including a stop of clock pulses by adding a stop detecting circuit for clock pulses which are counted by a watch dog timer. CONSTITUTION:A CPU1 outputs clock pulses 31 on the basis of the oscillation frequency of a crystal oscillator 2. The clock pulses 31 are inputted to the watch dog timer 3 and clock stop detecting circuit 4. The clock stop detecting circuit 4 detects a stop of clock pulses 31 and outputs a clock stop error signal 33. When a watch dog timer reset signal 32 is stopped, a watchdog error detection signal 34 is outputted and other error signals 35 of a parity check error, etc., are gated by an OR gate 5 to generate an error signal 36. The error signal 36 is ORed with a reset signal 35 to generate a CPU reset signal 38.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a self-diagnosis 111i circuit for a microcomputer board having an error detection function using a watchdog timer.

Techniques of invention + R-views and their problems] In general, a programmable controller that is implemented as one of the functions of a programmable controller monitors whether or not the program is being executed in the correct order. A watchdog timer is provided for this purpose. The watchdog timer is a timer that counts clock pulses from the central processing & [(hereinafter referred to as CPU) and outputs it after a certain period of time. An instruction is written to output a signal that resets the watchdog timer at regular intervals. Therefore, as long as the program is operating normally, the watchdog timer output, ie, the watch ladder error detection signal, is not output due to the periodic reset signal input to the watchdog timer. However, if the glogram goes out of control due to some abnormality, the It issue will stop, and once enough lock passes are counted, it will be detected as a watchdog error.

The self-diagnosis function includes random access memory (aA
There is also a parity check that detects whether there is an error υ in the binary code in order to check whether reading and writing 'lk of M) is normal.
This will be treated as another error.

When any one of the watchdog errors and other errors such as parity check errors occurs, the CPU is reset and an error is displayed by the light emitting element.

In the above self-diagnosis function, if the clock φ pulse from CP[J stops due to an abnormality in the crystal or some other reason, the watchdog timer will also stop working even though the CPU will naturally stop operating. Since it cannot be counted, the diagnostic function is lost, and errors cannot be detected even by other checking mechanisms. That is, an inconvenience may occur in which the abnormal state of stopping the tcPU is left unattended without any notification to the outside.

[Object of the Invention] In consideration of the above points, an object of the present invention is to provide a self-diagnosis circuit that detects and notifies system abnormalities and resets the CPU, even when the clock conflict halts. It is about providing.

[Summary of the invention]

In order to achieve the above object, the present invention adds a stop detection circuit for clock pulses counted by a watchdog timer to the conventional self-diagnosis circuit. CP(J
It is characterized by providing a circuit for resetting and displaying an error.

[Implementation sequence of the invention]

An embodiment of the present invention will be described below. As shown in FIG. 1, the CPU 1 outputs a clock pulse 31 using the oscillation frequency a of the crystal oscillator 2 as a reference. The clock pulse 31 is input to the watchdog timer 3 as a reference pulse, and is also manually input to the clock 1 stuck detection circuit 4, which is newly added in the present invention. Watchdog timer 3 is a watchdog timer reset signal 3 that is normally issued periodically by program instructions.
2, a reset is being applied, but when the watchdog timer contention reset signal 32 is interrupted, a watchdog timer error detection alarm signal 34 is output.

On the other hand, as will be described later with reference to FIG. 2, the clock stop detection circuit 4 detects that the clock pulse 31 has stopped and outputs a clock stop error signal 33. This watchdog error signal 34 and clock stop error signal 33
, and other error signals 35 such as parity number check errors are sent to the error-1 word 36 by the OR goo 15.
It can be summarized as The error signal 36 is a clear signal when the power is turned on, or the upper 7. Other CP such as requests from the system [J reset signal 37, OR gate 6
The CPU reset signal 38 is generated by

In addition, each error signal 33, 34, 35 is also transmitted to the error display circuit 7, and there may be a method of displaying each error type using a light emitting element (LED) or the like, or a method of displaying them all at once on a single display. It will be done.

Next, an example of a detailed configuration of the clock stop detection circuit 4 is shown in FIG. The input clock pulse 31 is split into two parts, one used as is and the other used as the clock pulse 41 inverted by the inverter 11. The principle is that each time the level of the clock pulse 31 is high and low, the capacitors 14A-H are repeatedly charged and discharged, and if the capacitors remain asleep or discharged, This is detected by the N0EL gate 15 and a clock stop error signal 33 is output. Charging of capacitors 14A and B is as follows:
The discharge takes place through diodes 12A-B and resistor 1
3A-B respectively.

First, consider the case where the clock pulse is normal.

At this time, the watchdog timer 3 operates normally as before, and outputs the watchdog error signal 34 only when the program execution is abnormal. On the other hand, in the IIJ design of the clock stop detection circuit 4, the light passing through the capacitor occurs almost instantaneously, but the discharge occurs with a time constant determined by the resistance value of the resistor 13A-B and the capacitor 14A-B. For example, a timing chart as shown on the left side of FIG. 3 is drawn. That is, if the discharge time constant is set appropriately long with respect to the period of the clock pulse, each level 4 of capacitors 14A and 1413
Since clock signals 2 and 43 are always kept in the high level range, the clock stop error signal 33, which is the output of the NOR gate 15, is not output. Therefore, when the clock pulse is normal, the self-diagnosis circuit works as before.

Next, consider the case where the clock pulse stops.

At this time, the watchdog timer 3 not only cannot count the time, but also does not execute the program due to the CPU stoppage, so the watchdog timer reset signal 32
It will no longer work and will no longer work.

On the other hand, as an example, the clock stop detection circuit 4
As shown in the right part of the time chart in the figure, if the clock pulse 31 were to stop when the level was low, the level 43 of the capacitor 14H would remain high, but the capacitor 14A would continue to discharge and its From the point at which level 42 changes to low, clock stop error signal 33 is output.

Even when the clock pulse 31 is stopped due to a low level, a clock stop error 1M signal 33 is output. Then, through this clock stop error signal 33Ia, 01 gates 5 and 6, Cl' U fi is reset.

The error is transmitted to the error display circuit 7, and the fact that an error has occurred is displayed to the outside.

If an abnormality occurs where the clock pulse stops,
This will cause the CPU to stop working and make it impossible to run Grogusim. Normally, program execution abnormalities are self-diagnosed by a watchdog timer, but when the clock pulse itself that is supposed to be used for counting by the watchdog timer has stopped, the 4th of the 7 stem abnormalities due to K.
fj cannot be issued. Therefore, by newly providing a circuit that detects the stoppage of the lock pulse as described in the embodiment of the present invention, the stoppage of the CPU due to the stoppage of the clock pulse can be monitored, and when an abnormality occurs, the same as in other self-diagnosis Table 4 hB is provided. niC
It becomes possible to reset the PU and notify the user by displaying an error.

[Effects of the Invention] The microcomputer board to which the present invention is applied is equipped with watchdog error detection and other self-diagnosis functions.
This is a serious failure that leads to a U-stop and should be placed above watchdog errors. As described in the present invention, the programmable controller system is capable of constantly identifying this abnormality in the self-diagnosis circuit, resetting the CPU, and notifying the outside of the error as soon as the abnormality occurs. / When incorporated into Sudem, system accidents can be minimized by making it possible to respond quickly after an error occurs.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of the self-diagnosis circuit portion of a microcomputer board that is the subject of the present invention, and FIG.
FIG. 3 is a circuit diagram showing a detailed embodiment of the clock stop detection circuit shown in the figure, and FIG. 3 is a flowchart illustrating changes in the signal level of each part of the clock stop detection circuit when the clock pulse changes from normal operation to a stopped state. . 1...Central processing unit (CPU) 2...Crystal oscillator 3...Watchdog timer 4...Clock stop detection circuit 5.6...OR gate 7...En-indication circuit 11
°...Inverter 12A-B...Diode 13A
-B...Resistor 14A・B...Capacitor 15・
...NOI is also a gate

Claims (1)

[Claims] A clock is generated from the central processing unit that performs program control calculations and is supplied to a watchdog timer for monitoring whether the program is being executed normally. A self-diagnosis circuit comprising a circuit for resetting the central processing unit when the signal stops, and a display circuit for displaying the reset circuit.