JPS60214051A - Detecting circuit for microcomputer runaway - Google Patents

Abstract

PURPOSE:To detect securely whether a basic clock is long or short and an oscillation stop by generating a counter reset signal, abnormal detection timing signal, and counter enable signal according to the timing of the basic clock, and controlling the counter. CONSTITUTION:The basic clock is inputted from a microcomputer 1 to a control signal generating circuit 3 to generate a counter reset signal, abnormality detection timing signal, and counter enable signal corresponding to the leading edge and trailing edge of the basic clock, and those are inputted to a counter 8 and the abnormal amplitude detecting circuit 8. An abnormal oscillation detecting circuit 5 monitors abnormality of the output of the counter 4 to detect abnormal oscillation and an oscillation stop detecting circuit 6 detects an oscillation stop. Outputs of those detecting circuits 5 and 6 are inputted to a signal composing circuit 7, which outputs a total abnormality detection signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microcomputer runaway detection circuit that detects an abnormality in the long or short cycle of a basic clock oscillated by a microcomputer and a stoppage of oscillation, thereby detecting runaway of the microcomputer.

In order to detect runaway in a microcomputer and promptly recover it, it is necessary to monitor the cycle of the basic clock oscillated by the microcomputer and detect whether it is always within the correct range.

For this purpose, there is a circuit called a watchdog timer as a basic clock cycle abnormality detection circuit conventionally used.

This charges a capacitor using the basic clock as the object to be inspected, and monitors the potential across it.While the basic clock is outputting normally, the potential across the capacitor also remains within a certain range, but the basic clock When the period of the basic clock becomes abnormally long, the potential across the capacitor drops below a threshold value, which is used to detect an abnormality in the period of the basic clock.

However, conventional runaway detection circuits or basic clock cycle abnormality detection circuits based on this principle have the drawback that they cannot detect when the basic clock cycle becomes abnormally short, that is, short cycle abnormalities. Ta.

The present invention has been made in view of this point, and is intended to be used when the basic clock period oscillated by a microcomputer becomes abnormally long beyond the permissible period (or indirectly, pulse width) range that can be considered to be in a normal operating state. In addition, it is an object of the present invention to provide a microcomputer runaway detection circuit that can similarly detect when the period becomes abnormally short, and furthermore, when the oscillation stops as a typical example of a long period abnormality.

Hereinafter, the structure, operation, and effects of the present invention will be explained through embodiments of the present invention shown in the accompanying drawings. First, FIG. 1 shows a principle or basic embodiment of the microcomputer runaway detection circuit of the present invention. It shows.

The object to be tested is the basic clock CP oscillated by the microcomputer 1. This basic clock CP is obtained by appropriately dividing the master clock PO oscillated by the external oscillator 2 attached to the microcomputer 1, and is not properly programmed. is executed, the pulse train generally has a duty of 50%.

Therefore, when the basic clock CP is logically at the "H'" level and the "°L°" level, its pulse width is the same, To.In this embodiment, first, although it oscillates, This pulse width or half cycle To is monitored to detect that the cycle is abnormal.

The detection of oscillation stop as a typical example of a long-period abnormality is, for example, one period of 2·T of the basic clock CP.

This is done by adding a margin time δ to the extent that .

On the other hand, in the present invention, such basic clock CP is first given to the control signal generation circuit 3. This control signal generation circuit 3 detects each rising edge and falling edge in the positive or negative direction of the basic clock CP, and generates a counter reset signal Sr corresponding to the rising edge and a counter reset signal Sr corresponding to the falling edge. generates a gate signal or an abnormality detection timing signal Sg, and these signals Sr
, Sg is not generated, the counter enable signal S! ! occurs.

Both the counter reset signal Sr and the counter enable signal Se are applied to a counter 8, which counts the master clock Pa while receiving the counter enable signal Se and sequentially outputs the result as a count output Sc. Of course, the counter reset signal S
When r is given, the count content Sc is reset to zero.

The abnormal oscillation detection circuit 5 constantly monitors the count output Sc of the counter 8 and outputs a counter enable signal Se.
After the generation of , check whether the time when the master clock Po reaches a predetermined numerical range coincides with the generation time of the detection timing signal Sg, or whether this count output is within a predetermined numerical range set by hardware. It is determined whether Sc is present or not.

Therefore, the detection timing signal S from the control signal generation circuit 3
If the count output Sc of the abnormal oscillation detection circuit 5 is outside the predetermined range when g is given, or if the time point at which the predetermined numerical range is counted is out of line with the generation timing of the detection timing signal Sg, then This is the result of either a long or short cycle abnormality occurring in the basic clock CP, and the abnormal oscillation detection circuit 5 outputs an abnormal oscillation detection signal Sa, and the signal synthesis circuit 7 outputs a comprehensive abnormality detection signal So. .

The count output Sc is also given to the oscillation stop detection circuit 6, and in the oscillation stop detection circuit 6, after the counter reset signal Sr falls, the above-mentioned time (2・To+
When the count value information corresponding to the elapse of the song interval T2 obtained by subtracting the pulse width α of the counter reset signal Sr from δ) is given, the oscillation stop detection signal Ss is output, similar to the previous abnormal oscillation detection signal Sa. It is then output as a comprehensive abnormality detection signal So via the signal synthesis circuit 7.

Conversely, if the count output Sc does not reach the above value for a considerable period of time, this means that the counter reset signal Sr has been generated within the above time 12, that is, the basic clock is oscillating with a rising edge. Therefore, of course, the oscillation stop detection signal Ss is not output.

”1 abnormal oscillation detection signal Sa and oscillation stop detection signal Ss
Although the present invention does not directly specify how to use the comprehensive abnormality detection signal SO synthesized from the It is to be.

This is because when some abnormality occurs in the basic clock CP, it is safest to return the microcomputer l to its initial state.

2 and 3 show a construction and a specific embodiment based on the principle embodiment shown in FIG. 1, and waveform diagrams of each part thereof.

The microcomputer 1 as an oscillator of the basic clock CP to be tested in FIG. 2 is in an operable state when the reset input is pulled up to the power supply potential or logic "H", which is approximately ground potential or logic "H". When the amount is withdrawn to "L", it shall be credited at least once. That is, the comprehensive abnormality detection signal or microcomputer reset signal SO is significant at logic "L". However, the present invention is not limited to this, and the form of the microcomputer reset signal So may be matched to the reset mode of the target microcomputer. Further, in this embodiment, a binary counter with an enable input is used as the counter 8, but its capacity and number of output bits may be appropriately selected so as to satisfy the following explanation.

The basic clock CP from the microcomputer 1 is inverted via the inverter 31 in the control signal generating circuit 3 and then applied to the integrating circuit 32. Therefore, as shown in the third row of FIG. 3, the signal waveform at point 0 in FIG. It becomes dull depending on the time constant. The waveform portion during this transitional period is shown as a straight line approximation for simplicity in the figure.

First, the counter reset signal Sr is generated by ANDing the 0 point signal and the basic clock CP using an AND gate 33. That is, the anime game 1.
If the high/low transition dark value at the input of 33 and the time constant by the resistor R and capacitor C are appropriately determined, as shown at point 0 in Fig. 3, from the rising edge of each period of the basic clock CP in the positive direction. A counter reset signal Sr that rises to logic "H" over a predetermined time α is obtained. Therefore, the counter 8 is once reset with each rising edge in the positive direction of each period of the basic clock CP.

On the other hand, at each falling edge of each period of the basic clock CP in the positive direction, a gate signal or a detection timing signal Sg to the abnormal oscillation detection circuit 5 is generated. That is, the 0 point signal and the basic clock CP are connected to the NOR gate 34.
Therefore, as shown at point 0 in FIG. 3, the detection timing signal Sg whose pulse width β is determined depends on the high/low transition threshold at the input of the NOR gate 34 and the time constant of the integrating circuit 32. generated. Conversely, in the case of this embodiment, each falling point of the basic tarokk CP for one shot is selected as the timing for outputting the detection result from the abnormal oscillation detection circuit 5, which will be described later. The threshold values of the AND gate 33 and the NOR gate 34 described above are schematically shown as broken lines across the transition period of the integral waveform in FIG.

The counter enable signal Se is generated by taking the NOR gate 35 between the counter reset signal Sr and the detection timing signal Sg.

Therefore, in this embodiment, the counter enable signal Se becomes a significant level "H" when both the counter reset signal Sr and the detection timing signal Sg are not at a significant logic level, that is, when they are at a logic "°L'". is shown at point 0 in FIG.

The counter 8 counts the mask clock PO when a significant counter enable signal Se with logic “H” is applied, but the count output Sc is input to the delay time setting circuit 51 in the abnormal oscillation detection circuit 5. The output signal waveform of the delay time setting circuit 51, indicated by the point ■ in FIG. 2, is shown in the fourth row from the bottom in FIG. It is defined as a pulse waveform that falls to logic "L" over an allowable time range γ in which the period of the clock cp can be considered normal.

As can be seen from the above-mentioned time relationships, the following time relationships are satisfied when the basic clock CP oscillates within a normal cycle range. However, the pulse width β of the detection timing signal Sg described above is set to be smaller than the pulse width γ of the point signal.

T1+α≦To≦71+a+y , , , , , ■β
γ・・・・・・・・・■ The output of the delay time setting circuit 51 is the detection timing signal Sg
Therefore, if the output of the delay time setting circuit 51 is logic "H" at the detection timing, it is determined that some kind of oscillation cycle abnormality has occurred in the basic clock CP. A logic "L" indicates that there is no abnormality in the oscillation cycle.This point will be explained in more detail.

As shown in the °゛normal' range in Fig. 3, as long as the basic clock cp satisfies the above equation 0, as is clear from Fig. 3, when the detection timing signal Sg is emitted, the delay time setting circuit The 0 point output of the AND gate 51 is always at the logic "L", so even if the detection timing signal Sg indicating that it is the detection timing is applied to the inputs of the AND gate 52, the output Sa of the AND gate 52 will be the same as before. In other words, the abnormal oscillation detection signal Sa shows the non-significant level "L".

In this embodiment, the signal synthesis circuit 7 for each abnormal signal is simply composed of a Nantes gate 71, and the output Sa of the AND gate 52 is added to the single power of this Nantes gate 71. As long as the abnormal oscillation detection signal Sa is at the non-significant logic level "L", the oscillation stop detection signal S applied to each input of the Nant gate 71 as described later
Since s is also at the non-significant logic level "L" at this point,
The overall abnormality detection signal or microcomputer reset signal So as the output of the signal synthesis circuit 7 maintains the same non-significant logic level "H" as before. In other words, the microcomputer 1 continues to operate without being reset. can continue.

However, if, for example, a disturbance occurs in the period of the basic clock CP, and one of the conditions in the above equation 0 goes out of order, resulting in To<TI+α . . . As shown in the "°" range, the detection timing signal Sg, which indicates the falling edge of the basic clock CP as the detection timing, turns on.
Even though the logic level has risen to "H" at point 2, since the predetermined time Tl has not passed since the fall of the counter reset signal Sr, the 0 point of the delay time setting circuit 51 is set at point 2, which is the same time as point 2. A situation arises in which the output is still at logic "H".

Then, since the inner inputs of the AND gate 52 both become logic "H'" at this point, the abnormal oscillation detection signal Sa as the output of the AND gate 52 becomes a significant level "H" as shown by the dots, and the AND gate 52 becomes logic "H". The overall abnormality detection signal So through the door] becomes a significant level "'L"' at point (3), and the microcomputer I is reset as expected.

Next, the "long cycle abnormality" in which the basic clock cycle becomes longer than a predetermined range will be explained.

Another condition of the 0 formula mentioned above is impaired, and To>TI+
Assuming that α + γ , ......■, as shown in Fig. 3, the range of "long cycle abnormality" indicates that even if the detection timing signal Sg is generated at time ■, it is already too late to set the delay time. The boiling output signal of the circuit 51 has already been maintained for a predetermined time α+T.
Since 1+γ has passed, a state occurs in which the temperature returns from °L" to H'" (point ■).

Then, at this point, similar to the previous short cycle abnormality,
As shown by points ■ and ■, the AND gate 52 performs an AND operation, and therefore, the abnormal oscillation detection signal Sa becomes a significant level "H", and the signal synthesis circuit 7 outputs a significant abnormality detection signal So at logic "L"'. is output, and one set of microcomputer l glue is calculated in the same way as before.

The oscillation stop detection circuit 6 also monitors the master clock count value Sc of the counter 8, and a count value 5c (T2) corresponding to the elapse of a predetermined time T2 after the fall of the counter reset signal Sr is input. At times, it outputs a significant oscillation stop detection signal Ss at logic "H".

The predetermined time T2 was briefly mentioned earlier, but in the case of this embodiment, for example, it is determined as follows.

T2-2・To δ-α 99. In other words, if the basic clock CP continues to oscillate at a cycle within the time T2 without stopping, the counter reset signal Sr will always be generated before the time T2 elapses, so the counter contents will be changed each time. Since it is cleared and the content of the counter never reaches the count value 5c (T2), the output Ss of the oscillation stop detection path 6 is also always at the logic "L" level.
keep it.

Therefore, under such conditions, the logical value of the abnormal oscillation detection signal Sa applied to the other input of the Nant's gate 71 becomes a factor that determines the output logical value of the Nand's gate 71, and as described above, If no cycle abnormality is found in the basic clock, the microcomputer 1 will not be reset.

However, on the other hand, "oscillation stop °" in the long cycle abnormal range in Figure 3
゛As shown in the abnormal part, although the basic clock CP rose at the beginning of the cycle,
・Even after To+δ time has elapsed, “H” is reached as shown by the point ■.
', the count information Sc to the oscillation stop circuit isometrically equal to the value 5c (T2
), and the output signal Ss from the oscillation stop detection circuit 6 becomes a significant level "Hpa" indicating the stop of oscillation, as shown by the point [phase].

This oscillation stop detection signal Ss only needs to be significant as a level, but it may have an appropriate pulse width ε as shown in FIG. 3, for example.

When this "H" level signal Ss is issued, the NAND game 71 in the signal synthesis circuit 7 inverts its output SO,
In FIG. 3, as indicated by a point (■), a "L" level abnormality detection signal SO is generated to reset the microcomputer 1.

Similarly, although not shown, even if the oscillation stops immediately after the basic clock falls, the count of the mask clock PO by the counter 8 will be reflected by the detection timing signal Sg of the pulse width β that is emitted in conjunction with the falling of the basic clock. The oscillation stop detection signal Ss is still generated, and the abnormality detection signal So, which is significant at logic "L", is output as the oscillation stop detection signal Ss is outputted as well. be done.

This concludes the explanation of the operation of the illustrated embodiment, but in the above, the delay time setting circuit 51 in the abnormal oscillation detection circuit 5 is only shown as a black box. This is because those skilled in the art can construct various configurations to satisfy the functions required of the delay time setting circuit 51, and the present invention does not directly specify this.

For example, the counter 8 that counts the mask clock PO
An appropriate gate array may be constructed for each bit output port of the counter 8 so that a logic "L"' is obtained at the final stage gate circuit output when the counter is counting a predetermined numerical range set in advance. 71 after inputting the counter reset signal Sr in the counter output port group.
The inversion of the output port that inverts the output after the elapse of time may activate a monostable multi-pie break connected thereto, and a pulse lasting for a predetermined time γ may be obtained as its output. Of course, there are other possible configurations of each company as mentioned above.

This also applies to the oscillation stop detection circuit 6.
Connect an appropriate monostable multi-occurrator to the output port of the counter that inverts the output after 12 hours, or use the signal line of the output port as the oscillation stop detection circuit itself and input it directly to the signal synthesis circuit 7. It's okay.

Further, in this synthesis circuit itself, if the outputs of the abnormal oscillation detection circuit 5 and the oscillation stop detection circuit 6 are of an oven collector type, for example, a simple wired OR can be used instead of the Nant gate 71.

Of course, in the above logic operation, switching between positive logic and negative logic is obvious. For example, when the basic clock CP rises in the negative direction, the counter reset signal Sr is obtained, and when the basic clock CP falls in the negative direction, the counter reset signal Sr is obtained ( That is, the detection timing signal sg may be obtained at the transition from logic "L" to "H".

In any case, as explained above, according to the present invention, even if the program goes out of control due to unexpected external noise, etc., the basic clock will be able to operate both above and below the period range in the normal state, and will not oscillate again. With regard to the stoppage of the microcomputer, it is possible to reliably detect the stoppage of the microcomputer, and if necessary, the microcomputer can be quickly set, so that serious accidents caused by runaway can be avoided.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a schematic diagram of an embodiment of the principle of a microcomputer runaway detection circuit according to the present invention, FIG. 2 is a schematic diagram of a slightly more specific embodiment, and FIG. FIG. 6 is an explanatory diagram of main part signal waveforms of the second illustrated embodiment. In the figure, 1 is a microcomputer, 2 is a master clock oscillator, 3 is a control signal generation circuit, 4 is a counter, 5 is a basic clock abnormal oscillation detection circuit, 6 is a basic clock oscillation stop detection circuit, and 7 is a signal synthesis circuit. , Po is the master clock, CP is the basic clock, Sr is the counter reset signal, Se is the counter enable signal, Sg is the detection timing signal, Sa is the abnormal oscillation detection signal, Ss is the oscillation stop detection signal, SO is the comprehensive abnormality detection It's a signal.

Claims (1)

[Scope of Claims] A microcomputer runaway detection circuit that detects a cycle abnormality in a basic clock from a microcomputer obtained by dividing a master clock oscillated by an oscillator, and detects runaway of the microcomputer; In response to the rise and fall of the basic clock, a counter reset signal and an abnormality detection timing signal are generated, respectively, and after the counter reset signal is generated,
a control signal generation circuit that generates a counter enable signal at least until the abnormality detection timing signal is generated; a counter that counts; an abnormal oscillation detection circuit that detects a cycle abnormality of the basic clock based on the count output of the counter and outputs the detection result using the abnormality detection timing signal; an oscillation stop detection circuit that detects that there is no logic inversion in the clock based on the count value of the counter and generates an oscillation stop detection signal; A microcomputer runaway detection circuit comprising: a signal synthesis circuit that generates a comprehensive abnormality detection signal when either signal becomes a significant signal representing an abnormality; and a signal synthesis circuit that generates a comprehensive abnormality detection signal.