SU1285591A1 - Counting device with checking - Google Patents

Description

112

The invention relates to computing and can be used in discrete devices, including two meters as components and nodes.

The purpose of the invention is to increase the functional reliability by eliminating the parasitic effect of transient

processes, especially when using asynchronous counters, to work the counting device with control.

The drawing shows a diagram of a two-bit counting device with a control.

The proposed device contains an input bus 15 counter 2, ele20

25

thirty

ment And 3, element OR 4, decoder 5, triggers 6-9, elements AND 10-13, element 14, additional elements AND 15-18, output bus 19, low-pass filter 20, additional trigger 21, elements NOT 22- 25, weekends 26 and 27.

For a two-bit bottom meter 2, the decoder 5 has four outputs.

The inputs of the element I. OR 4 are connected to the codes of elements AND 10-13, the first - the fourth outputs of the decoder .5 are connected respectively to the inputs of elements NOT 22-25, the outputs of which are connected respectively to the first inputs of elements AND 10-13, the second inputs which are connected respectively - indirectly with the direct outputs of the triggers, the input bus 1 is connected to the first inputs of elements 3 and 14, the outputs of the counter 2 are connected to the inputs of the decoder 5, the first to the fourth outputs of the decoder 5 are connected respectively to the first inputs of elements 15 15-18, the outputs which connection respectively, with the installation inputs into the unit of flip-flops 6-9, the outputs of the AND elements 16-18 and 15 are connected respectively with the installation inputs to the zero of the flip-flops 6-9, the direct outputs of which are connected respectively to the secondary inputs of the AND elements 16-18 and 15, the output element OR 4 is connected

Let the device be reset. This means: in the counter 2, O (initial initial state) is written, 1 is written in the trigger 6, O is written in the trigger 6, O is written in the trigger 21 (the setting circuits are not shown)

In this case, the logical 1 from the first output of the decoder 5, corresponding to the initial state, passed through the element NOT 22, closes the element AND 10 and at its output will be zero, the signal-al.

At the same time, the logical 1 from the output of the trigger 6 prepares the element AND 16 for passing the signal of the second output of the decoder 5. At the same time, of all the elements 15-18 it is only the element 16 that is prepared to pass the signal.

When the next leading edge of the positive counting pulse arrives from the bus 1, the counter 2 passes into the next state. At the corresponding output of the decoder 5, logical 1 appears, which, having passed the elements of AND 16, sets the trigger 6 to the zero state, and the trigger 7 - to the single state. . Logic 1 from the output of the trigger 7 to the input of the element OR 4 does not arrive, as it is blocked by a logical O from the output of the element NOT 23.

Similarly, there is a further change in the state of the counter.

When a pulse arrives on bus 1 in meter 2, especially when using asin40 as the last

45

with the output bus 19 and with the input of the filter of the chronic counter, transient processes occur, which lead to the appearance of some of the lower frequencies in the outputs, the output of which is connected to the output bus 26 and

0

0

five

0

connected to the counting input of the counter 2.

The device works as follows.

Each state of counter 2 corresponds to a single state of one of the triggers 6–9, and these states are identified by a decoder 5 by generating a logical 1 signal at the corresponding output.

Let the device be reset. This means: in the counter 2, O (initial initial state) is written, 1 is written in the trigger 6, O is written in the trigger 6, O is written in the trigger 21 (the setting circuits are not shown)

In this case, the logical 1 from the first output of the decoder 5, corresponding to the initial state, passed through the element NOT 22, closes the element AND 10 and at its output will be zero, the signal-al.

At the same time, the logical 1 from the output of the trigger 6 prepares the element AND 16 for passing the signal of the second output of the decoder 5. At the same time, of all the elements 15-18, only the element 16 is prepared to pass the signal.

When the next leading edge of the positive counting pulse arrives from the bus 1, the counter 2 passes into the next state. At the corresponding output of the decoder 5, logical 1 appears, which, having passed the elements of AND 16, sets the trigger 6 to the zero state, and the trigger 7 - to the single state. . Logic 1 from the output of the trigger 7 to the input of the element OR 4 does not arrive, as it is blocked by a logical O from the output of the element NOT 23.

Similarly, there is a further change in the state of the counter.

When a pulse arrives on bus 1 in meter 2, especially when using asin0 as the last

five

 transient processes, which lead to the appearance at the outputs of some elec

cops And 10-13, respectively, at the output of the element OR 4 short sexes

the second input element And 14, output

which is connected to the clock input

trigger 21 direct and inverse output IvIpilkov.

the dyes of which are connected according to Gwen Filter 20 is set to time s.ano with the output schnb) st 27 and with the second

the input element And 3, the output of which

long transient sa with „o, j; (,, i.e. if

And 10-13 elements of the element and, respectively, at the output of the element OR 4 short positive and IvIpylkov.

long transient sa with „o, j; (,, i.e. if

process-ele31

ment or 4, the pulse duration exceeds the C ioiyc ° through the filter 20 and goes to the bus 26. The appearance of the pulses on the bus 26 indicates that due to the aging of elements or any other reasons, the transient time in the counter 2 exceeds the permissible, but counter 2 still remains operable. If the transition time is equal to cs, then at the output of element 14 a logical 1 appears, which translates the trigger 21 into a single state. In this case, the And 3 element is closed, the pulse counting stops, and an alarm signal appears on the bus 27. The single state of one of the triggers 6-9 indicates the last correct state of counter 2, and the erroneous state is fixed in the counter 2 itself.

The duration of the input pulse bus 1 must be greater than

VNIIPI Order 7535/57 Circulation 899.

Random polygons pr-tie, Uzhgorod, st. Project, 4

855914

Moikc is the time required for triggering 21.

In the event of a fault, for example, at the transition of the first pulse, the unit potential disappears at the first output of the decoder 5 and does not appear at the second output of the decoder 5.

In this case, the trigger 6 does not reset 10 seconds to zero and zero, the potential at the first output of the decoder 5 leads to the appearance of a unit at the output of the AND 10 element and, respectively, at the output of the OR 4 element, the trigger 21 is set to 1, the AND 3 element is closed and An error signal appears on bus 27.

and as a counter 2, a counter with any conversion factor can be used, it is important that the number of outputs of the decoder 5 corresponds to the number of operating states of the counter 2.

Subscription

Claims (1)

COUNTING DEVICE WITH CONTROL, containing the input bus, counter, decoder having p-outputs, p + 2 elements. And, η triggers, η elements NOT, and an OR element, the inputs of which are connected to the outputs of η elements AND, each i-th output of the decoder (i = 1, · ..., η) is connected to the input of the ί-th element NOT, the output which is connected to the first input of the ΐth element And, the second input of which is connected to the direct output of the ίth trigger, the input bus is connected to the first inputs of the n + 1st and n + 2nd elements AND, the outputs of the counter are connected to the inputs of the decoder, characterized in that, in order to increase functional reliability, a low-pass filter, an additional trigger and an additional η are introduced into it n elements And, every i-th output of the decoder ^! connected to the first input of the i-th additional element And, the output of which is connected to the installation input to the i-ro trigger unit, the output of each i-ro additional element And, except the first, is connected to the installation input to zero of the i-1st trigger, output the first additional element And is connected to the installation input to the ηth trigger zero, the direct output of each i-ro trigger, except for the nth, is connected to the second input of the i + 1th additional element And, the direct output of the nth trigger is connected to the second the input of the first additional AND element, the output of the OR element is connected input of the lowpass filter, whose output is connected to the clock input of the additional flip-flop ^ inverted output is connected to the second input of n + 1-th AND gate whose output is connected to the counting input of the counter. Q <e N3 □ About