JPS5816353A - Monitoring system for fault of computer - Google Patents

Abstract

PURPOSE:To monitor the falt of a computer over a wide range for a computer fault monitoring system using a monitor timer, by setting an allowabl lower limit value to the time interval for production of a reset signal and then having a comparison of said lower limit value. CONSTITUTION:Both the allowable upper and lower limit values are set to the integrated value CNT of a counter 21 which is incorporated into a monitor timer 2' and integrates the pulses produced by the clock. The reset signal is applied periodically to the counter 21 to clear this counter when the computer to be monitored is normal. Then an alarm signal is delivered from the timer 2' when the integrated value of the counter 21 is larger than the allowable upper limit value or when the value CNT corresponding to the producing interval of the reset signal is smaller than the allowable lower limit value.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system for monitoring computer abnormalities using a monitoring timer.

In the conventional method of monitoring computer abnormalities, as shown in the block diagram of the abnormality monitoring configuration in Fig. 1, the pulses emitted by the clock CLK built in the monitoring timer 2 are constantly integrated by the counter 21, and the pulses generated by the clock CLK built in the monitoring timer 2 are constantly integrated, and the pulses are accumulated at about 1/2 of the allowable upper limit value. integrated value (=calculator i that occurs at time 2 Carano+7 cent signal R8T
The total value CNT of the counter 21 is cleared in response to the reset signal R8T, and after the reset signal R8T disappears, the total value CNT of the counter 21 is restarted. The value LILIM is compared with the comparator 23, and when CNT exceeds ULIM, the monitoring time is set? 2 outputs an alarm signal ARM.

However, abnormalities in computers that should be monitored include not only processing congestion and inoperability, but also problems caused by fixed-period timers TM built into computers, for example.
If the timer TM generates a reset signal RAT every fixed period of time, the timer TM may advance abnormally due to the influence of noise, and as a result, the reset signal RAT may be generated at a much shorter time interval than planned. The comparative detection method using the allowable upper limit value ULIM chisel could not detect such computer abnormalities.

The present invention has been devised to eliminate the above-mentioned drawbacks, and by setting and comparing a permissible lower limit value for the reset signal generation time interval, even when the reset signal generation time interval is abnormally short, this can be fixed. Provides a method for monitoring and generating alarms.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of a computer abnormality monitoring configuration according to an embodiment of the present invention, which differs from the conventional abnormality monitoring configuration block diagram of FIG. 1 in the allowable upper limit ULIM of the integrated value CNT of the counter 21, The limit setter 3'''!7'C also provides the allowable lower limit value LLI'M from the computer, and both of these allowable values are used together to perform abnormality monitoring.

For permissible reasons, either the counter integrated value or the time interval between reset signal generation may be used as the substance of the lower limit value, but there should be a linear relationship between the counter integrated value and the elapsed time, except for special situations at the time of reset. In this case, although the color integrated value is more advantageous in handling *p for measurement, comparison, etc. than the elapsed time, the counter integrated value will be used in the following explanation.

FIG. 3 is an explanatory diagram of various signal generation situations according to an embodiment of the present invention, and FIG. 4 is an enlarged view of the configuration of this embodiment.

When the fixed period timer TM detects the arrival of a fixed period, the signal CPI
When the computer 1 receives this signal as an input signal, it starts the user task TK as shown in FIG. Inside task TKII'i, the reset signal ratio is 8.
Take T.

Returning to FIG. 3, at time S the computer l sends a reset signal R8T.
(P in this case) is output and the integrated value C of the counter 21 is output.
After lowering NT to clear level G (CNT = OJ, as the time TIME elapses again, the pulse of the built-in clock CLK in the monitoring timer 2' is calculated. If it operates normally including the periodic timer TM.

The next reset signal R8T (in this case Pt
) to clear the integrated value CNT, the monitoring timer 2' does not output the alarm signal ARM. However, after outputting the reset signal R8T (in this case, P), the computer 1 continues to output the reset signal R8T until the integrated value CNT of the counter 21 reaches the allowable upper limit value ULIM due to processing congestion or failure to output. Since this does not occur, when CNT exceeds ULIM (point E1), the monitoring timer 2' outputs an alarm signal ARM.

Next, when the computer 1 abnormally emits the seven-bit signal R15T, it outputs the reset signal kLsT (in this case, P) to clear the cumulative value CNT of the counter 21, and then the counter 21 outputs the cumulative value CNT. When the CNT continues to advance to 81 points, the condition that the fixed period timer TM has passed an apparent predetermined time is established and the CPI signal is generated, and the already mentioned task TK sets the reset signal ratio ST (here P+). To emit.

Since the cumulative value CNTII'iCT is reached between the generation of the reset signal P9 and the generation of the reset signal P4, and the allowable lower limit value LLIMK of the counter 21 has not even been reached, the monitoring timer 2' outputs the alarm signal ARM.

The mechanism of these operations will be explained using diagram M4. After user task TK resets ff1 R, ST output, if there is a traffic jam in the middle of processing P'RC in task TK due to an error in computer 1, even if there is a 1st-order fixed period timer error, lt
Since task TK is not activated on a regular basis, the reset signal R
8T cannot be output and only one hour has passed, that is, counter 2
Only the integrated value CNT of 1 continues to increase. Monitoring timer 2'
Internally, a counter 21 inputs the allowable upper limit values tu, iM to the terminal B of the comparator 23-2, inputs the allowable lower limit value LLiM to the terminal C of the comparator 23-1, and integrates the pulses of the clock 22.
The integrated value CNT is input to the terminal A of the comparator 23-1 and the terminal A of the comparator 23-2. The ratio f unit 23-1 has two human power CNT, LLl, M, CNT>LLiM
If 'o'CNT (LLIM, 'l#' is set respectively, and the comparator 23-2 is set by two people.
, about ULIM CNT) ULIM has the function of outputting 1# CNT and ULIM 7
is "0" or -) CNT) ULIM, the monitoring timer 2' outputs an alarm signal ARM.

According to the above, the upper limit value can be given by setting the switch SW installed in the limit setter 3' to the remote 'fL@' and starting the limit value transfer task LIMTR, or by setting the switch SW to the local L side. If this is set, the set values of the lower limit value setting means 3] and 32 are manually inputted to the monitoring timer 2'.

Indication time interval of reset signal generation, that is, counter 21
For example, set the integrated value CNT to one-half of the allowable upper limit value ULIM.
, Further, if the allowable upper limit value ULIM is selected to be one-half of the maximum cumulative value of the counter 21, a considerable resolution WP can be obtained, and binary expression is also easy, which is advantageous.

Since there are various possible causes of the abnormality, it is difficult to uniformly specify the allowable lower limit value LLIM1 for determination.
When starting computer 1, an appropriate value is given to ULIM and zero is given to LLiM, and as a result, the computer is operated with only the allowable upper limit value monitored, as in the conventional method, and the computer is operated stably. Once it is confirmed that the limit setting device 3' or the limit value transfer task LIMTR can be used, the allowable lower limit value LLiM may be specified.

Thereafter, this allowable lower limit value will be used for determination. Of course, it is also possible to modify or change the lower limit value.

According to the present invention, a lower limit value is determined based on the tolerance of the integrated value of the counter that integrates the pulses generated by the clock built in the monitoring timer, and when the computer to be monitored is normal, a reset signal is given to the counter at regular intervals. When the counter integrated value becomes larger than the allowable upper limit value or the counter integrated value corresponding to the reset signal generation time interval becomes smaller than the allowable lower limit value, the monitoring timer outputs an alarm signal. Computer abnormalities can be monitored over a wide range.

[Brief explanation of drawings]

Figure 1 is a block diagram of a computer abnormality monitoring configuration according to a conventional method, Figure 2 is a block diagram of a computer abnormality monitoring configuration according to an embodiment of the present invention, and Figure 3 is a block diagram of a computer abnormality monitoring configuration according to an embodiment of the present invention. Each signal generation The situation explanatory diagram, FIG. 4, is an enlarged view of the configuration of an embodiment according to the present invention. 1...Calculation-12...Conventional method monitoring timer, 2'.
...6 Monitoring timers according to embodiments of the present invention, 3, 3'...
・Limit setter, 21... counter, 22 river clock,
23°23'... Comparator, 23-1.23-2...
Bottom, upper limit comparator. 31.32...Tolerance upper and lower limit setting means, LJLIM
...Tolerance upper limit value, LLIM...Tolerance lower limit value, G...
・Counter clear value, approximately 8T'...Reset signal, A
RM...Alarm signal, CNT...Counter integrated value, P,, P+Pm*P4...Reset signal %
S+kl,'h! ... Reference time, CT ... Reference integrated value %SW ... Changeover switch, TK ... User task, LIMTkL ... Limit value transfer task, CPI
...Timer wash signal, TM... Fixed period timer. f 1・Figure 9' 12 mouth

Claims (1)

[Claims] In a computer abnormality monitoring method using a monitoring timer, the monitoring timer includes at least a clock and a counter. A second comparator is built in, and the counter integrates the output pulses of the clock, outputs d calculation 11 (CNTJ, and outputs the integrated value + CNT to the first comparator) and the allowable lower limit value (i, L).
im) is input, the integrated value (CNT7 and the allowable lower limit tULIM) is input to the second comparator, and when the computer sends a reset signal to the counter at regular intervals, the integrated value (color/ri) is input. CNT), but the first comparator reaches LLIM before clearing. If the size of the CNT is determined and it becomes LLIM (LLIM)CNT, the first condition is satisfied, and the second condition is determined to be satisfied when the second comparator always determines the size of the ULIM and CNT and becomes ULIM (eNT). An IT computer abnormality monitoring system characterized in that the monitoring timer outputs an alarm signal ARM when either of two conditions is satisfied.