JPH0736161B2 - CPU abnormality detection device - Google Patents

Description

The present invention relates to a CPU abnormality detection device.

As shown in FIG. 1, the conventional CPU abnormality detection device has a CPU
1, a monitoring timer 2, a detection number counter 3, and an OR gate 4.

The CPU 1 incorporates a timer reset signal output program for outputting a timer reset signal at regular intervals when it is operating normally according to a predetermined program, and as shown in FIG. 2 when the CPU reset signal is input. An initialization program for initializing a predetermined program is incorporated in.

Next, the operation of the CPU abnormality detection device will be described. When the power is turned on, the detection number counter 3 is reset by the power-on reset signal. After the power is turned on, when the CPU1 is operating normally according to the specified program, the timer reset signal is output from the CPU1 and the monitoring timer 2 is reset periodically by this timer reset signal. No reset signal is input to CPU1.

However, when normal operation is not performed due to an abnormality and the timer reset signal is no longer output from the CPU 1, the monitoring timer 2 times up and outputs a pulsed CPU reset signal, and this pulsed CPU reset signal is output from the OR gate 4.
Is input to the CPU 1 through the above, whereby the predetermined program is initialized based on the initialization program, and the predetermined program is executed again. Further, the pulsed CPU reset signal output from the monitoring timer 2 is input to the detection number counter 3, and the detection number counter 3 counts the number of appearances of the pulsed CPU reset signal.

Then, the above operation is repeated each time an abnormality occurs, and when the number of occurrences of the abnormality, that is, the count value of the detection number counter 3 reaches a predetermined value, the detection number counter 3 outputs a CPU reset signal of a constant level. A constant level CPU reset signal is input to the CPU 1 through the OR gate 4 and holds this state. Therefore, the CPU1 is in a stopped state.

As described above, the conventional configuration has a configuration in which the CPU 1 stops functioning when the counter value of the detection number counter 3 reaches a certain value, and therefore the original abnormality occurs (hardware component failure, Other than (program failure), that is, when a temporary abnormality occurs due to external noise such as lightning surge or when a malfunction such as the monitoring timer 2 occurs, it is unlikely to be repeated many times in a short time. Even for a temporary error, the number of times it occurred in the past is added up, and there was the inconvenience that the CPU1 stopped functioning even though it was not the original error.

Therefore, it is an object of the present invention to provide an abnormality detecting device for a CPU that can prevent a functional stop due to a temporary abnormality that is not considered to be repeated in a short time.

As shown in FIG. 5, the CPU abnormality detecting device of the present invention includes a monitoring timer 2 for outputting a CPU reset signal in a pulse form at the time-up, and a pulsed CPU reset signal output from the monitoring timer 2. A detection number counter 3 that counts the number of occurrences and continuously outputs a CPU reset signal when the count value reaches a certain value, and sends a timer reset signal to the monitoring timer 2 at regular intervals during execution of a predetermined program. Timer reset signal generating means 1A,
When the CPU reset signal is input, the judging means 1B for judging whether or not the present time has passed a certain time since the previous abnormality occurrence time, and to the detection number counter 3 when the judgment result of this judging means 1B is affirmative The present invention is characterized by including a counter reset signal generating means 1C for sending a counter reset signal and a CPU 1'having an initializing means 1D for initializing the predetermined program when the CPU reset signal is input.

An embodiment of the present invention will be described with reference to FIGS. 3 and 4. This CPU abnormality detection device, as shown in FIG. 3, has a CPU 1 ', a monitoring timer 2, and a detection number counter 3
, And OR gates 4 and 5.

The CPU1 'incorporates a timer reset signal output program for outputting a timer reset signal at regular intervals when it is operating normally according to a predetermined program, and is shown in FIG. 4 when the CPU reset signal is input. As described above, the current time is input and stored, and it is determined whether or not the current time has passed a certain time since the previous abnormality occurrence time, and when the determination result is YES, a counter reset for resetting the detection number counter 3 Output a signal, then initialize the specified program, and the above judgment result
When NO, the initialization program for directly initializing the predetermined program is incorporated.

Next, the operation of the CPU abnormality detection device will be described. When the power is turned on, the detection number counter 3 is reset by the power-on reset signal. After turning on the power, if CPU1 'is operating normally according to the specified program, CPU1'
Since the timer reset signal is output from the monitor timer 2 and the monitor timer 2 is periodically reset by the timer reset signal, the monitor timer 2 does not expire and the reset signal is not input to the CPU 1 '.

However, if normal operation is not performed due to an abnormality and the CPU 1 ′ stops outputting the timer reset signal, the monitoring timer 2 times out and outputs a pulsed CPU reset signal. It is input to the CPU 1 ′ through 4, thereby inputting and storing the current time based on the initialization program, and it is determined whether or not the current time has passed a certain time compared with the previous abnormal occurrence time, and a certain time has passed. If so, the counter reset signal for resetting the detection counter 3 is output, and then the predetermined program is initialized. If the predetermined time has not elapsed, the predetermined program is immediately initialized and the predetermined program is executed again. Further, the pulsed CPU reset signal output from the monitoring timer 2 is input to the detection number counter 3, and the detection number counter 3 counts the number of appearances of the pulsed CPU reset signal.

Then, the above operation is repeated each time an abnormality occurs, and when the number of occurrences of the abnormality, that is, the count value of the detection number counter 2 reaches a predetermined value, the detection number counter 3 outputs a CPU reset signal of a constant level. A certain level of CPU reset signal is input to CPU1 'through OR gate 4,
CPU1 'is in a stopped state.

Here, the difference in reset operation between the CPU reset signal generated from the monitoring timer 2 and the CPU reset signal generated from the detection counter 3 will be described. In the case of the output from the monitoring timer 2, the CPU reset signal is only issued for a short time, and the CPU1 signal is output immediately after the fall of the CPU reset signal.
, But the CPU reset signal from the detection number counter 3 is continuously generated and the CPU reset signal does not fall, so that the CPU 1 cannot restart the operation.

As described above, in this embodiment, since the detection number counter 3 is reset when a certain time elapses from the previous abnormality occurrence time to the current abnormality occurrence time, the original abnormality occurrence (hardware component failure, program Other than (defective), that is, when a temporary abnormality occurs due to external noise such as lightning surge or when a malfunction such as the monitoring timer 2 occurs, it is unlikely to be repeated many times in a short time. Abnormalities are not accumulated, and it is possible to prevent the CPU 1 ′ from stopping its function.

Here, the relationship between the configuration of resetting the detection number counter 3 and the point of being able to prevent the functional stop due to a temporary abnormality which is not considered to be repeated in a short time will be described. In other words, by utilizing the fact that the monitoring timer 2 is not reset when the program is abnormal, a pulse CPU reset signal is output from the monitoring timer 2 to initialize the program of CPU1
When CPU1 is restored to normal operation by restarting, the CPU1 program is initialized by the monitoring timer 2, and CPU1 is restarted. Since it is impossible to restore the normal operation of the CPU1 by initializing the program of the CPU1, the detection count counter 3 counts the number of resets of the CPU1 and reaches the predetermined value. The counter 3 outputs a continuous CPU reset signal to keep the reset state of the CPU 1 and prohibit the re-operation of the CPU 1 so as to prompt the repair of the CPU 1. Furthermore, it is not an abnormality caused by the CPU1 itself, but repeated in a short time, such as an abnormality in the CPU1 due to external factors such as lightning surge, that is,
In the case of a temporary abnormality that is unlikely to occur again even if the program of CPU1 is initialized, it is not necessary to repair CPU1. In this case, it is not convenient to stop the operation of CPU1. It is a thing. However, even if an abnormality occurs due to a lightning surge or the like, it will occur many times over time, and if this number is counted by the detection number counter 3, the detection number counter 3 finally counts a constant value. In the conventional example, the operation of the CPU 1 is stopped at this time, but in the present embodiment, the detection number counter 3 is reset when a fixed time has elapsed from the previous abnormality occurrence time. Since the configuration is adopted, it is possible to prevent the function of the CPU 1 from being stopped due to the repeated repetition of an abnormality that is unlikely to be repeated in a short time, such as an abnormality caused by a lightning surge or the like.

As described above, according to the CPU abnormality detection device of the present invention, a CPU reset signal is output in a pulse form from the monitoring timer by utilizing the fact that the monitoring timer is not reset when the program is abnormal, and the CPU program is initialized. The CPU can be restored to normal operation by restarting it.

In addition, the monitoring timer initializes the CPU program to
Even if the PU is restarted, if the CPU program initialization is repeated due to repeated abnormalities, the CPU program initialization cannot restore normal operation. Therefore, when the detection count counter counts the number of CPU resets and reaches a predetermined value, a continuous CPU reset signal is output from the detection count counter to keep the CPU reset state and prohibit CPU restart. Since it has a configuration, it can be prompted to repair the CPU.

Furthermore, it is not likely that the abnormality is caused by the CPU itself, but it is thought that the abnormality will occur again even if the CPU program is initialized, such as when a CPU abnormality occurs due to an external factor such as lightning surge, that is, the CPU program is initialized. If there is no temporary abnormality, the CPU does not need to be repaired. In this case, it is inconvenient to stop the CPU operation. Even if an abnormality such as a lightning surge occurs, it will take time. This will occur many times, and if this number is counted by the detection number counter, the detection number counter will eventually count a fixed value.
Although the operation of U is stopped, in the present invention, since the detection number counter is reset when a certain time has elapsed from the previous abnormality occurrence time, a short time such as the occurrence of an abnormality due to a lightning surge or the like occurs. It is possible to prevent the function of the CPU from stopping due to the repetition of a temporary abnormality that is unlikely to be repeated.

[Brief description of drawings]

FIG. 1 is a block diagram of a conventional example, FIG. 2 is a flow chart of its CPU, FIG. 3 is a block diagram of an embodiment of the present invention, FIG. 4 is a flow chart of its CPU, and FIG. It is a block diagram showing. 1 '... CPU, 1A ... timer reset signal generating means, 1B
...... Judgment means, 1C ...... Counter reset signal generation means,
1D ... Initializing means, 2 ... Monitoring timer, 3 ... Detection counter

Claims (1)

[Claims] 1. A monitoring timer for outputting a CPU reset signal in a pulse form at the time-up, and the number of occurrences of a pulsed CPU reset signal output from the monitoring timer is counted, and when the count value reaches a certain value. A detection number counter for continuously outputting a CPU reset signal, timer reset signal generation means for sending a timer reset signal to the monitoring timer at regular intervals during execution of a predetermined program, and
When a CPU reset signal is input, a judging means for judging whether or not the present time has passed a certain time since the previous abnormality occurrence time, and a counter reset signal to the detection frequency counter when the judgment result of this judging means is affirmative An abnormality detecting device for a CPU, comprising: a CPU having a counter reset signal generating means for sending the CPU and an initialization means for initializing the predetermined program when the CPU reset signal is input.