JPH05173841A - Monitor circuit for watchdog timer - Google Patents

Abstract

PURPOSE:To correctly detect whether both a corresponding central processing unit 1 and a watchdog timer operate always normally or not through simple circuit configuration. CONSTITUTION:In a circuit constituted of the watchdog timer 2 connected to the central processing unit 1 and a capacitor voltage detecting means 4 which compares the voltage of a capacitor 3 connected to the watchdog timer 2 with the prescribed voltage and informs the central processing circuit of this result, the pulse P of a prescribed period is generated from the central processing unit 1 to the watchdog timer 2, and simultaneously, the watchdog timer 2 is provided with a means to generate a reset pulse RP to the central processing unit l when the pulse from the central processing unit 1 does not come, and further, the capacitor voltage detecting means 4 includes the means to inform the central processing unit 1 of information based on relation between the voltage of the capacitor and the prescribed reference voltage and informing whether the watchdog timer 2 operates normally or not.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monitor circuit for a watchdog timer in a computer, and more specifically, it detects a malfunction, runaway, infinite loop or the like of the computer to detect an abnormal operation of the computer. The present invention relates to a monitor circuit of a watchdog timer that can detect accurately and effectively.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 9, a central processing unit 1 composed of an appropriate micro computer or the like always operates normally in a predetermined processing circuit, control circuit or the like. A device for detecting whether or not the central processing unit is present and stopping the central processing unit when the operation of the central processing unit is abnormal or driving an alarm means for warning the operator of the abnormal operation is also used.

A watchdog timer 2 is known as an example of such a device. The watchdog timer 2
Is directly connected to the central processing unit 1, and specifically, the central processing unit 1 causes the watchdog timer to generate a predetermined pulse P having an appropriate frequency. The pulse is also called a watchdog timer pulse or a pumping pulse.

On the other hand, the watchdog timer 2 usually has a mechanism for generating a reset pulse RP for resetting and initializing the central processing unit 1 when the power is turned on. When the predetermined pulse P is not input from the central processing unit, the central processing unit 1
It has a function of generating a reset pulse RP by determining that a failure has occurred in the function of.

That is, in the watchdog timer 2, a predetermined pulse P is output from the central processing unit after the power is turned on.
Is not input, or the pulse P has been input for a predetermined period of time, but if the pulse P is not input even after a predetermined time elapses from a certain time point, the function of the central processing unit 1 is impaired. When the power supply is turned off or an alarm is generated to warn the operator, the central processing unit 1 is repaired or replaced.

[0006]

In the central processing unit monitor circuit using the watchdog timer 2, the function of the central processing unit is surely checked. As for itself,
There is no check system, and in some cases, the watchdog timer 1 is out of order, and the watchdog timer 2 is reset even if the predetermined pulse P is not output from the central processing unit 1. Pulse RP
Is not output, the central processing unit 1 continues to operate with a failure, and as a result, the central processing unit runs out of control,
The problem of entering an infinite loop occurs.

Therefore, an object of the present invention is to solve the problems in the prior art, and with a simple circuit configuration, both the central processing unit 1 and the watchdog timer 2 are normally operated normally. Whether or not there is a failure in at least one of the functions, it is possible to immediately stop the operation of the circuit concerned, or display to warn the operator. By providing the above, it is possible to provide a watchdog timer monitor circuit capable of preventing an accident from occurring.

[0008]

In order to achieve the above-mentioned object, the present invention adopts the technical constitution as described below. That is, the central processing unit, the watchdog timer connected to the central processing unit, the voltage of the capacitor connected to the watchdog timer is compared with a predetermined reference voltage, and the capacitor voltage for notifying the central processing unit of the result. In the circuit configured by the detection means, the central processing unit generates a pulse of a predetermined cycle to the watchdog timer, and in the watchdog timer, the pulse from the central processing unit is Means is provided for generating a reset pulse to the central processing unit when it has stopped, and further, the capacitor voltage detection means, the watchdog timer from the relationship between the voltage of the capacitor and a predetermined reference voltage. Monitor of watchdog timer including means for notifying the central processing unit of information as to whether it is operating normally It is a road.

[0009]

Since the monitor circuit of the watchdog timer according to the present invention adopts the technical configuration as described above, the function of the central processing unit 1 is checked by the watchdog timer 2 by the conventional method. In addition, the function of the watchdog timer 2 is
It is possible to constantly check whether or not the function is normally operated by monitoring the voltage of the capacitor provided in the device using an appropriate capacitor voltage detecting means.

Further, in the watchdog timer monitor circuit according to the present invention, the abnormality of the capacitor voltage is recognized by monitoring the output information of the capacitor voltage detecting means by the central processing unit 1. In this case, the central processing unit 1 operates an appropriate alarm means to notify the operator or the like that the watchdog timer 2 is out of order, so that the watchdog timer 2 can be repaired or replaced. Executed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a watchdog timer monitor circuit according to the present invention will be described below in detail with reference to the drawings. That is, FIG. 1 is a schematic block diagram of a monitor circuit of a watchdog timer according to the present invention. In a circuit composed of a capacitor voltage detecting means 4 for comparing the voltage of the capacitor 3 connected to the timer 2 with a predetermined reference voltage and notifying the result to the central processing unit,
The central processing unit 1 generates a pulse P of a predetermined cycle to the watchdog timer 2 and, in the watchdog timer 2, when the pulse from the central processing unit 1 stops, Means 5 for generating a reset pulse RP is provided for the arithmetic unit 1, and further, the capacitor voltage detecting means 4 is arranged so that the watchdog timer 2 operates normally from the relationship between the voltage of the capacitor and a predetermined reference voltage. It is a watchdog timer monitor circuit including means for notifying the central processing unit 1 of information as to whether or not it is operating.

In the watchdog timer monitor circuit according to the present invention, the capacitor voltage detecting means 4 determines whether the watchdog timer is operating normally from the relationship between the voltage of the capacitor and a predetermined reference voltage. It is preferable that the information processing means is constituted by means for converting the information on whether or not it is a binarized signal and notifying it to the central processing unit. In particular,
As shown in FIG. 2, it may be configured by a comparator 40. In this case, the non-inverting input terminal of the comparator 5 has a reference voltage V _ref set to an appropriate voltage level.
Is input, and the voltage value of the capacitor is input to its inverting input terminal.

As described above, the watchdog timer monitor circuit according to the present invention can monitor the voltage of the capacitor continuously and continuously after the central processing unit 1 is powered on. It is possible to reliably check whether or not the function of is operating normally. The reference voltage V _ref of the comparator 405 in this example is
If the power supply of the monitor circuit of the watchdog timer is V _CC, it is, for example, 1/2 V _CC .

The operation of each part in the above specific example will be described with reference to the timing waveform chart of FIG. First, the watchdog timer 2 used in this example has a circuit configuration as shown in FIG. 3, for example. That is, the watchdog timer 2 has a base connected to the input 31 for receiving the pulse P input from the central processing unit 1, its collector is connected to one end of the capacitor 33, and its emitter is A transistor 41 connected to the other end of the capacitor 33 and grounded, a collector of the transistor 41 connected to an inverting input end, and an appropriate reference voltage V _ref connected to a non-inverting input end. And its output is input to the monitor circuit of the central processing unit 1 and one end thereof is connected to one end of the capacitor together with the collector of the transistor 41 and the other end is the power supply V. It is composed of a resistor connected to _CC and having an appropriate resistance value.

In the above configuration, when the central processing unit 1 sends a pulse P having a predetermined frequency as shown in the waveform (a) to the watchdog timer 2,
At the "H" level portion of the pulse, the transistor 32 is turned on.
Since N, the electric charge charged in the capacitor 33 up to that point is discharged, and therefore the voltage at the node N drops rapidly. However, since the transistor 32 is turned off immediately, the capacitor 33 is turned off. Since it is charged by V _{CC, the} voltage at the node N becomes as shown by b-1 in the waveform diagram (b).

By repeating such an operation, the voltage of the capacitor 33 shown at the node portion N is changed to that shown in FIG.
The waveform will change as shown in FIG. Therefore, for example, the waveform (b) is compared with the reference voltage V _ref by the comparison circuit 34, and when the waveform (b) exceeds the reference voltage V _ref , an “H” level signal is output from the comparison circuit 34. When it is output, a binarized signal as shown in the waveform (c) of FIG. 4 is obtained.

When the waveform (c) is input to an appropriate monitor circuit provided in the central processing unit 1 and the waveform (c) synchronized with the pulse P is obtained, the watchdog timer 2 By configuring so that it is determined that the central processing unit 1 is functioning normally,
When the pulse P is not transmitted, the waveform (b) becomes a fixed waveform as shown in b-2, and as a result, the waveform (c) also alternates between "H" level and "L" level. Since the waveform is fixed at "H" level without taking the waveform, the function of the central processing unit is checked by determining that the state is that the function of the central processing unit has become abnormal. I can do things.

In this embodiment, the reference voltage V _ref of the comparison circuit 34 can be set to 1/2 V _CC , for example. That is, the capacitor voltage detecting means in the above-mentioned specific example uses the relationship between the voltage of the capacitor and a predetermined reference voltage to convert the information as to whether the watchdog timer is operating normally into a binary signal. It shows an example constituted by means for converting and notifying to the central processing unit.

Further, in addition to the above example, the capacitor voltage detecting means in the present concrete example converts the analog voltage of the capacitor into a digital value by using an appropriate analog / digital converter, and the digital value thereof is obtained. A means for comparing the value with a predetermined reference voltage, notifying the result to the central processing unit, and performing a function check of the central processing unit 1 in the monitor circuit of the central processing unit 1 good.

Next, another specific example of the watchdog timer monitor circuit according to the present invention will be described. That is, in the above-mentioned specific example, if the predetermined pulse P is not generated from the central processing unit 1, the reset pulse RP is generated from the watchdog timer 2 to reset the central processing unit 1. However, in such a specific example, when the central processing unit 1 fails, a spare circuit such as a spare CPU is usually provided in advance, and an appropriate switch mechanism is used to provide protection from the failed central processing unit. It is common practice to switch to this central processing unit.

However, it is not preferable in terms of arithmetic processing to perform such switching operation frequently, and it is more preferable if the function of the watchdog timer 2 can be checked without using the reset pulse RP if possible. It is a thing. Further, resetting the central processing unit may destroy the data which has already been executed and is in the middle of the arithmetic processing, and it is preferable to avoid the reset operation as much as possible.

On the other hand, even if the central processing unit 1 stops the generation of the above-mentioned pulse P for some reason,
In the case of a soft error, the function is often returned to a normal state by inputting the reset pulse RP a plurality of times. In other words, if the central processing unit 1 is an obstacle in terms of hardware, it does not return to a normal state even if the reset pulse is added,
It is necessary to switch to a spare circuit or replace the central processing unit itself, but in the case of a software error, there is a possibility of returning by a reset pulse,
It is preferable to give the central processing unit whose function has failed a plurality of recovery opportunities.

For example, when a certain central processing unit 1 causes a failure in the function and the generation of the pulse P is stopped, the recovery opportunity is not given only once, but a plurality of times, for example, at least twice, preferably. It is preferable to efficiently recover the central processing unit by giving recovery opportunities three times or more. Therefore, as a second specific example of the present invention, the reset pulse RP is not directly input from the watchdog timer 2 to the central processing unit 1, but is associated with the voltage detection and comparison means of the capacitor, This is a watchdog timer monitor circuit configured to restore the central processing unit by applying reset pulses RP to the central processing unit 1 a plurality of times.

FIG. 5 shows the configuration of the monitor circuit of the watchdog timer according to this example. 5 is basically the same as the block diagram of FIG. 1 except that the reset pulse RP from the watchdog timer 2 is not input to the central processing unit 1 and the capacitor voltage is different. This is the point input to the detection means 4. FIG. 6 is a block diagram showing an example of a circuit configuration suitable for the capacitor voltage detecting means 4 used in this example.

That is, an input end S1 to which the pulse P output from the central processing unit 1 is input is provided at one end of the first capacitor C1, and the other end of the capacitor C1 is a first end. The first diode D1 is connected to one end of each of the diode D1 and the second diode D2.
The other end of the second diode D2 is grounded, and the other end of the second diode D2 is connected to one end of the second capacitor C2 and one end of the third diode D3.

The other end of the second capacitor C2 is grounded, and the other end of the third diode D3 is connected to the watchdog timer 2 and the central processing unit 1 at predetermined time intervals. When the pulse P is not input, it is connected to the input terminal portion S2 to which the reset pulse RP continuously generated at a predetermined interval is input. On the other hand, one end of the second capacitor C2 and one end of the third diode D3 are connected to the inverting input end of the comparator 40, and an appropriate non-inverting input end of the comparator 40 is connected. The reference voltage adjusted to the voltage is input.

The output of the comparator 40 is connected to an appropriate monitor circuit provided in the central processing unit, or an appropriate switching means for switching between the central processing unit and a spare central processing unit and an appropriate switching unit. It is connected through a monitor circuit. The capacitances of the capacitors C1 and C2 used in FIG. 6 are such that the output of the comparator 40 is not inverted even when the reset pulse RP is input to the input terminal portion S2 at least twice as described later. That is, it is desirable that the watchdog timer 2 is selected so as to be maintained at a voltage level that can indicate that the function of the watchdog timer 2 is normal.

FIG. 7 shows the waveforms in the above circuit. The waveform (a) in FIG. 7 is the waveform of the pulse P output from the central processing unit 1 to the watchdog timer 2. Further, the waveform (b) shows the change in the voltage charged in the capacitor C2 at the node N when the pulse of the waveform (a) is input. When the voltage exceeds the reference voltage V _ref , the output of the comparator 40 becomes “H” level and the waveform (c) is obtained.

That is, when the waveform (c) is at "H" level, it can be judged that the watchdog timer 1 is normal and the central processing unit 1 is also functioning normally. It should be noted that if some trouble occurs in the function of the central processing unit 1 from a certain point in time and the pulse P is no longer output to the watchdog timer 2 from the central processing unit, the watchdog timer 2 keeps the predetermined period. After the lapse of time, the reset pulse RP of "L" level is output.

As a result, the electric charge charged in the second capacitor C2 is discharged through the third diode D3, so that the voltage of the node portion N decreases as shown in the waveform (b). When the voltage becomes lower than the reference voltage V _ref , the output of the comparator 40 changes from “H” level to “L” level. By the way, in the present specific example, as described above, when the function of the central processing unit 1 temporarily fails, the central processing unit 1 is applied with the reset pulse a plurality of times. The operation is performed as shown in the waveform diagram of FIG. 8 because it gives the chance of recovery by the number of times.

That is, first, in the state where the first reset pulse RP1 in FIG. 7 has not been input yet,
As shown in the waveform diagram (a) of FIG. 8, if the first reset pulse RP1 is input, the second capacitor C
The voltage of the node portion N indicating the charging voltage of 2 decreases, but the decrease degree is under the condition that the voltage falls below the reference voltage only when the reset pulse RP is input a plurality of times as described above. Since the voltage is set, the voltage drop is small as shown in the waveform diagram (b), and the voltage of the node N becomes lower than the reference voltage only after the third reset pulse RP3 is input. ..

That is, in this example, while the first and second reset pulses RP1 and PR2 are being input, as shown in the waveform diagram (c), the watchdog timer 1 and the central processing unit 1 are connected. Is assumed to be functioning normally. However, when the third reset pulse RP3 is input, the output of the comparator 40 changes from the “H” level to the “L” level, so that the recovery chances have already been given twice. Since there is no output of the pulse P, it is judged that the central processing unit has completely failed, and the central processing unit is switched to a spare central processing unit or a warning is displayed to the operator to repair or replace the central processing unit. Will be executed.

[0033]

Since the monitor circuit of the watchdog timer according to the present invention adopts the above-mentioned configuration, both the central processing unit 1 and the watchdog timer 2 are constantly operated by a simple circuit configuration. It makes it possible to accurately detect whether or not it is operating normally, and if at least one of the functions fails, immediately notify the operator of the status, or stop the operation of the circuit. By providing a display for warning, a watchdog timer monitor circuit that can prevent the occurrence of an accident can be obtained.

In the watchdog timer monitor circuit according to the present invention, the central processing unit 1 functions normally without inputting a reset pulse directly to the central processing unit. When the function is abnormal, or when the function of the central processing unit 1 is abnormal even though the watchdog timer 2 is functioning normally, the function of the central processing unit 1 and the watchdog timer 2 is not determined. It is possible to easily detect any of the abnormal states.

Further, according to the present invention, the watchdog timer circuit is provided with an insurance function, and when the central processing unit fails, the spare central processing unit is switched to. Has the effect of achieving stabilization.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a principle and a specific example of a monitor circuit of a watchdog timer according to the present invention.

FIG. 2 is a block diagram showing a specific example of a monitor circuit of a watchdog timer according to the present invention.

FIG. 3 is a block diagram showing an example of a watchdog timer that can be used in the monitor circuit of the watchdog timer according to the present invention.

FIG. 4 is a waveform diagram in the specific example shown in FIG.

FIG. 5 is a block diagram showing another specific example of the monitor circuit of the watchdog timer according to the present invention.

FIG. 6 is a block diagram showing an example of a voltage comparison means used in the specific example of FIG.

FIG. 7 is a waveform chart in the specific example of FIG. 6.

FIG. 8 is another waveform diagram in the specific example of FIG.

FIG. 9 is a block diagram showing an example of a conventional watchdog timer circuit.

[Explanation of symbols]

 1 ... Central processing unit 2 ... Watchdog timer 3 ... Capacitor 4 ... Voltage comparison circuit 40 ... Comparator 5 ... Reset pulse generation circuit

Claims (7)

[Claims] 1. A central processing unit, a watchdog timer connected to the central processing unit, and a voltage of a capacitor connected to the watchdog timer are compared with a predetermined reference voltage, and the result is notified to the central processing unit. In the circuit composed of the capacitor voltage detecting means for generating a pulse of a predetermined cycle from the central processing unit to the watchdog timer, in the watchdog timer, from the central processing unit Means for generating a reset pulse to the central processing unit in the case where the pulse of the capacitor is not provided, and the capacitor voltage detecting means is further configured to detect the watch from the relationship between the voltage of the capacitor and a predetermined reference voltage. A watch characterized by including means for notifying the central processing unit of information as to whether or not the dog timer is operating normally. Dog timer monitor circuit. 2. The capacitor voltage detecting means converts the information as to whether or not the watchdog timer is operating normally into a binary signal based on the relationship between the voltage of the capacitor and a predetermined reference voltage, and converts the information into a binarized signal. 2. The watchdog timer monitor circuit according to claim 1, wherein the monitor circuit comprises means for notifying the central processing unit. 3. The capacitor voltage detecting means comprises means for converting an analog voltage of the capacitor into a digital value, comparing it with a predetermined reference voltage, and notifying the result to the central processing unit. The watchdog timer monitor circuit according to claim 1. 4. The capacitor is charged from the central processing unit to the watchdog timer in response to an input pulse,
4. The watchdog timer monitor circuit according to claim 1, wherein the watchdog timer is discharged by a reset pulse generated by the watchdog timer. 5. If the watchdog timer does not transmit the pulse to the watchdog timer after the watchdog timer has generated a reset pulse to the central processing unit, the central processing unit is reset. 5. The watchdog timer monitor circuit according to claim 1, further comprising means for displaying a failure of the arithmetic unit. 6. If the watchdog timer does not transmit the pulse to the watchdog timer from the central processing unit after generating the reset pulse to the central processing unit a plurality of times. 6. The watchdog timer monitor circuit according to claim 5, further comprising means for displaying that the central processing unit has failed. 7. The charging voltage of the capacitor is configured such that it can be maintained at a voltage lower than the predetermined reference voltage after the reset pulse is generated a plurality of times. Watchdog timer monitor circuit.