JPH05181710A - System for monitoring central processing unit - Google Patents

Abstract

PURPOSE:To prevent the generation of a fault by individually detecting whether all of a central processing unit(CPU), a watchdog timer and a CPU monitoring means are normally driven or not. CONSTITUTION:The CPU 1 is provided with a means for generating a prescribed synchronous pulse P to the watchdog timer 2 and the timer 2 is provided with a reset pulse generating means for generating a reset pulse RP to the CPU 1 when the pulse P does not arrives from the CPU 1. In addition, the CPU monitoring means 3 is provided with a function for monitoring a reset pulse RP outputted from the timer 2 and judging whether the function of the CPU 1 is normally operated or not from information obtained from a reset pulse RP. An alarming means 4 is driven in response to an output outputted from the means 3 and indicating the abnormality of the function of the CPU 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit in various arithmetic circuits using the central processing unit and the control of the periphery thereof, and a monitor system for monitoring whether or not the arithmetic circuit is functioning normally. More specifically, the central processing is performed by simultaneously detecting the failure, runaway, or infinite loop of the central processing unit including a computer, etc., and simultaneously monitoring the function of the monitor circuit for monitoring the function of the central processing unit. The present invention relates to a monitor system for a central processing unit capable of effectively and accurately detecting an abnormal operation of a processing circuit centered on the device.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 9, a central processing unit 1 composed of an appropriate micro computer or the like always operates normally in a predetermined processing circuit, control circuit or the like. A device for detecting whether or not the central processing unit is present and stopping the central processing unit when the operation of the central processing unit is abnormal or driving an alarm means for warning the operator of the abnormal operation is also used.

A watchdog timer 2 is known as an example of such a device. The watchdog timer 2
Is directly connected to the central processing unit 1, and specifically, the central processing unit 1 causes the watchdog timer to generate a predetermined pulse P having an appropriate frequency. The pulse is also called a watchdog timer pulse or a pumping pulse.

On the other hand, the watchdog timer 2 usually has a mechanism for generating a reset pulse RP for resetting and initializing the central processing unit 1 when the power is turned on. When the predetermined pulse P is not input from the central processing unit, the central processing unit 1
It has a function of generating a reset pulse RP by determining that a failure has occurred in the function of.

The predetermined pulse is transmitted by the central processing unit 1.
While the normal operation is being executed, the watchdog timer 2 is constantly transmitted at a predetermined interval.
It may be output every time a predetermined arithmetic processing is completed in the central processing unit 1. That is, in the watchdog timer 2, when the predetermined pulse P is not input from the central processing unit after the power is turned on, or the pulse P is input for a predetermined period, a predetermined time is passed from a certain time point. When the pulse P is not input even after the passage of time, further, the central processing unit 1 goes out of control, and an abnormally large number of pulses are transmitted from the central processing unit 1, and the watchdog timer 2
Then, when a state in which it cannot be determined that a normal pulse has been input occurs, it is determined that the function of the central processing unit 1 has failed, and the power is turned off or an alarm is generated. Then, the operator is warned and the central processing unit 1 is repaired or replaced.

[0006]

In the monitor circuit of the central processing unit using the watchdog timer 2, the functional tick of the central processing unit is certainly performed.
As for the watchdog timer 2 itself, there is no check system, and in some cases, the watchdog timer 1 is out of order and the predetermined pulse P is not output from the central processing unit 1. Regardless of
The reset pulse RP is not output from the watchdog timer 2 and the central processing unit 1 continues to operate with a failure, and as a result, the central processing unit runs out of control or enters an infinite loop. Occurs.

In particular, in recent years, a central processing unit composed of a microcomputer, a CPU and the like has been widely used for various controls in vehicles such as automobiles. However, it is easily affected by heat generation, etc., and failures often occur and noise is often input, and there are many problems in maintaining stable operation. In particular, a control circuit used in a recent air bag control system is required to be strictly controlled, and further, it is necessary to be managed so that a failure state will never occur.

However, in the conventional control arithmetic circuit centering on the central arithmetic unit, the function of accurately determining whether or not the function of each circuit is operating normally is insufficient, and each circuit is insufficient. Since there was no function to check whether the monitor circuit for monitoring the state of the function of (1) was operating correctly, it was insufficient to construct a control circuit that realizes fail-safe.

Therefore, an object of the present invention is to solve the problems in the prior art, and with a simple circuit configuration, both the central processing unit 1 and the monitoring circuit around the central processing unit can operate normally at the same time. It provides a system that can accurately monitor whether or not it is operating, and if at least one of the circuit functions fails, immediately notify the operator by activating the alarm means. The present invention provides a monitor system for a central processing unit, which allows the central processing unit itself to judge a functional abnormality in the processing circuit while calling attention.

[0010]

In order to achieve the above-mentioned object, the present invention adopts the technical constitution as described below. That is, a central processing unit, a watchdog timer connected to the central processing unit, a central processing unit monitor for detecting whether or not the functions of the central processing unit connected to the watchdog timer are normally operating. And a warning means connected to the central processing unit monitoring means, wherein the central processing unit generates a pulse of a predetermined cycle from the central processing unit to the watchdog timer. The watchdog timer is provided with a reset pulse generating means for generating a reset pulse to the central processing unit when a predetermined pulse from the central processing unit stops. Further, the central processing unit monitor means monitors the reset pulse output from the watchdog timer and The central processing unit has a function of judging whether the function of the central processing unit is operating normally from the information obtained by Is a monitor system of a central processing unit configured to be driven in response to an output indicating that

[0011]

The monitoring system for the central processing unit according to the present invention employs the technical configuration as described above, so that the central processing unit 1 monitors the output pulse P of the watchdog timer 2. At the same time, the watchdog timer 2 generates a reset pulse RP when there is no input of the pulse P from the central processing unit, and the reset pulse RP is monitored by the central processing unit monitoring means 3 to perform the central processing. It is possible to constantly check whether the functions of the device 1 are operating normally.

On the other hand, the function of the central processing unit monitor means 3 is that the central processing unit 1 generates a pseudo reset pulse RP which is close to the reset pulse RP and inputs the pseudo reset pulse RP into the central processing unit monitoring means 3. By determining whether or not the arithmetic unit monitor means 3 executes a predetermined operation, it is determined whether or not the central arithmetic unit monitor means 3 is functioning normally.

Further, when it is judged whether the functions of the watchdog timer 2 and the central processing unit monitor means 3 are operating normally, the output of the pulse P is intentionally stopped from the central processing unit 1 side. Further, the reset pulse is prevented from being input to the reset pulse input terminal portion of the central processing unit 1, and in such a state, the reset pulse RP is transmitted from the watchdog timer 2 via the central processing unit monitoring means 3. It is executed by monitoring whether or not it is returned to the central processing unit 1.

In the monitoring system for the central processing unit according to the present invention, when at least one of the functions of the central processing unit 1, the watchdog timer 2 and the central processing unit monitoring means 3 becomes abnormal. The alarm means activates an appropriate alarm to notify an operator or the like that any one of the above circuits has a failure, so that the operation for repairing or replacing the circuit is executed.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a watchdog timer monitor circuit according to the present invention will be described below in detail with reference to the drawings. That is, FIG. 1 is a schematic block diagram of a monitor system for a central processing unit according to the present invention, in which the central processing unit 1, a watchdog timer 2 connected to the central processing unit, and the watch are shown. A central processing unit monitor means 3 for detecting whether or not the function of the central processing unit 1 connected to the dog timer 2 is operating normally; and an alarm means 4 connected to the central processing unit monitoring means 3. In the monitor system constituted by, the central processing unit 1 generates a pulse P having a predetermined period as described above to the watchdog timer from the pulse output end 8 of the central processing unit. The watchdog timer 2
In this case, there is provided reset pulse generating means 11 for generating a reset pulse RP to the central processing unit 1 when the predetermined pulse P from the central processing unit 1 stops.

The reset pulse RP is input to the reset pulse input terminal 9 of the central processing unit 1. Further, the central processing unit monitor means 3 is connected to the watchdog timer, monitors the reset pulse RP output from the watchdog timer 2, and at the same time, the central processing unit 1 is monitored from the information obtained by the reset pulse RP. Has a function of judging whether or not the function of the central processing unit 1 is operating normally, and the alarm means 4 indicates from the central processing unit monitoring means 3 that the function of the central processing unit 1 is abnormal. A monitoring system for a central processing unit configured to be driven in response to an output.

The configuration of the pulse P monitor circuit of the watchdog timer according to the present invention is not particularly limited, but the pulse P output from the central processing unit 1 is input to the pulse P monitor. When continuously input at appropriate intervals, it is determined that the function of the central processing unit 1 is operating normally, and whether the pulse P is not input even after a predetermined time elapses. When it is not recognized as a normal pulse P even if it is input, it is determined that the function of the central processing unit 1 is abnormal, a reset pulse RP is output, and the reset pulse RP resets the central processing unit 1. It is input to the pulse input terminal 9.

In the monitoring system for a central processing unit according to the present invention, when the reset pulse RP is output once, it is determined that the function of the central processing unit 1 is abnormal and the power source of the central processing unit is turned off. Instead of shutting off or repairing or replacing the central processing unit, the central processing unit 1 often recovers even if it is in an abnormal state when it is reset and restarted. Therefore, the reset pulse RP is repeated a plurality of times.

Therefore, there is no problem if the reset pulse RP is first output and the function of the central processing unit 1 is restored to normal, but even if the reset pulse RP is output, the pulse P from the central processing unit 1 is output. If does not occur, the reset pulse RP is output again and the situation is observed, and this operation is repeated at least a plurality of times, for example, about 10 times.

A specific example of the reset pulse RP generating means in the watchdog timer 2 is shown in FIG. 1. For example, the first one having one end to which the pulse P from the central processing unit 1 is inputted. And a second capacitor C2 having one end connected to the other end of the first capacitor C1 and the other end grounded, and one end of the second capacitor C2 A comparator 12 having an inverting input terminal portion connected thereto and a non-inverting input terminal portion connected to an appropriate reference power source is provided, and includes an amplifier circuit 13 connected to an output of the comparator 12. Then, the reset pulse RP is output from the output side of the amplifier circuit 13.

The comparator 12 and the amplifier circuit 13
An appropriate capacitor 14 and constant current source 15 for the wiring connecting
May be provided. In the reset pulse generating means of the watchdog timer 2, the pulse P
By comparing the voltage charged in the second capacitor C2 (that is, the potential of the node portion N) with a predetermined reference voltage in the comparator 12, the voltage is changed by the absence of the input of the pulse P. When the voltage is lower than the predetermined reference voltage, it is determined that the operation of the central processing unit 1 is abnormal, and the reset pulse RP is output.

Next, the structure of the central processing unit monitor means 3 according to the present invention will be described. The central processing unit monitor means 3 outputs information for judging whether the function of the central processing unit is normal or abnormal based on the number of reset pulses RP output from the watchdog timer 2.
A specific example of the configuration is shown in FIG. The central processing unit monitoring means in FIG. 1 includes a pulse-voltage converting means 5 for generating a voltage corresponding to the number of reset pulses output from the watchdog timer during a predetermined period, and the pulse-voltage converting means 5. Voltage comparing means 6 for comparing the output voltage with a predetermined reference voltage, and the voltage comparing means 6
The alarm means drive means 7 is driven in response to the output from the CPU indicating that the function of the central processing unit is abnormal.

The pulse-voltage converting means 5 in the central processing unit monitoring means 3 is connected to the reset pulse RP output end of the watchdog timer 2 via a diode D1. The pulse-voltage converting means 5 according to the present invention is not particularly limited, but any configuration is possible as long as it has a function of generating a voltage according to the number of input of the reset pulse RP input within a unit time. It can also be used in circuits with.

For example, the pulse-voltage converting means may have a function of generating a voltage in response to a change in the frequency of the reset pulse, and may be composed of a capacitor, and the capacitor may be provided with the plurality of resets. It may be configured to input a pulse and output the charging voltage. When the voltage according to the reset pulse RP output by the pulse-voltage converting means 5 is compared by the voltage comparing means 6, and the voltage output from the pulse-voltage converting means 5 exceeds a predetermined reference voltage value, , It is judged that the function of the central processing unit 1 is abnormal, and the alarm means driving means 7
Is operated to activate appropriate alarm means connected to the alarm means drive means 7, for example, a warning lamp, an alarm sound generating means and the like.

In the present invention, the alarm means driving means 7
Output directly from the predetermined input terminal section 16 of the central processing unit 1.
May be input to the CPU and the abnormality may be judged by an appropriate judgment circuit in the central processing unit. That is, in the present invention, the function of the central processing unit 1 cannot be normally restored although the reset pulse RP is output a plurality of times to give the central processing unit a plurality of recovery opportunities. It is determined to be in a state.

Further, in the present invention, there is a problem whether or not the function itself of the pulse-voltage converting means 5 is operating normally. Therefore, a monitor for checking the function of the pulse-voltage converting means 5 is required. It is necessary to provide a circuit, and as one of the means, a pseudo pulse FRP corresponding to the reset pulse RP is supplied to the pulse-voltage converting means 5 from the monitor terminal section 10 provided in the central processing unit 1. It has such a configuration.

That is, in this example, a pseudo pulse FRP that is the same as or close to the reset pulse RP is output from the monitor terminal 10 of the central processing unit 1.
Is supplied to the input end of the pulse-voltage conversion means 5 via the second diode D2, and the pseudo pulse F
The RP is used to forcibly check whether or not the function of the pulse-voltage converting means 5 operates normally.

Therefore, the pseudo pulse FRP may be any pulse as long as the pulse-voltage converting means 5 operates. The check operation must be avoided when a predetermined reset pulse RP is output from the watchdog timer, and it is preferable that the arithmetic processing circuit centered on the central processing unit 1 be powered on. Immediately after the execution, it is preferable to carry out the operation when the predetermined arithmetic processing is not started.

As described above, the monitor system circuit of the central processing unit according to the present invention has both circuits of the central processing unit 1 and the pulse-voltage converting means 5 continuously continuously after the central processing unit 1 is turned on. It is possible to reliably check whether or not the function of is operating normally. The reference voltage V _ref of the comparator 12 in this example is assumed to be V _{CC when} the power source of the monitor circuit of the watchdog timer is V _CC .
It is preferably 1/2 V _CC .

The operation procedure of the monitor system of the central processing unit according to the present invention will be described with reference to the flow charts of FIGS. FIG. 2 illustrates an operation procedure for checking the function of the central processing unit 1 in the monitor system for the central processing unit according to the present invention.
It is assumed that the microcomputer of 1 is out of control for some reason. First, the state concerned is the central processing unit 1.
When it occurs in step (1), the central processing unit 1
The output of the pulse P is stopped from the pulse P output terminal section 8 of.

Next, in step (2), when the reset pulse RP generating circuit of the watchdog timer 2 detects that the pulse P is not input, and the pulse P is not input for a predetermined period. At the same time that the reset pulse RP is output to, the reset pulse RP is generated in a constant cycle up to a predetermined number of times unless the pulse P is input in step (3).

In step (4), the output of the reset pulse RP is input to the pulse-voltage conversion means 5,
The reset pulse RP in the pulse-voltage conversion means
The voltage proportional to the number, frequency, etc. of
The voltage is compared with a predetermined reference voltage, and when the voltage exceeds the reference voltage value, it is determined that the function of the central processing unit 1 is abnormal, and the alarm means driving means 7 is driven, In step (5), the appropriate alarm means 4 connected to the alarm means driving means 7, such as an alarm lamp and an alarm sound generating means, is activated.

In step (6), the operator executes the inspection and repair of the central processing unit 1 based on the alarm. See also Figure 3
3 is a flow chart for executing the function check of the pulse-voltage conversion means 5 in the present invention. First, in step (1), a predetermined monitor pulse is output from the monitor check terminal unit 10 of the central processing unit 1. Then, in step (2), the monitor pulse is input to the pulse-voltage converting means 5.

In step (3), it is judged whether or not the alarm of the alarm means 4 is driven. If the alarm of the alarm means 4 is driven, the function of the pulse-voltage conversion means 5 operates normally. If the alarm of the alarm means 4 is not driven (step (4)), it is determined that the function of the pulse-voltage conversion means 5 is not operating normally (step (5)). Is.

FIG. 4 shows another specific example of the central processing unit monitor means 3 in the present invention. That is, the pulse-voltage conversion means 5 of the central processing unit monitor means 3 described above is
The voltage of the predetermined reference power source 40 and the watchdog timer 2
And a first comparator 41 for comparing the voltage of the reset pulse RP output from
42 connected to the output of the transistor 42, a first capacitor 43 connected to the collector of the transistor 42, a second capacitor 46 connected to the other end of the capacitor 43 via diodes 44 and 45, and It comprises a second comparator 48 for comparing the voltage value of the second capacitor 46 and the voltage value of the reference power source 49, and further has an alarm means driving means 7 driven by the output of the second comparator 48. There is something.

In the circuit structure, the first comparator 41 to the second capacitor 46 constitute the pulse-voltage converting means 5, and the second comparator 48 corresponds to the voltage comparing means 6. Is. In the pulse-voltage converting means 5, the reset pulse RP input from the watchdog timer 2 is amplified to sequentially charge the second capacitor 46 via the first capacitor 43, and the charging voltage is Although it is input to the second comparator 48, in the state where the reset pulse RP does not come, the charge of the second capacitor 46 is changed to the resistance 49.
The electric charge of the capacitor is reduced by discharging through the capacitor.

In the above-described central processing unit monitor system according to the present invention, it is possible to check whether or not the function of the central processing unit monitor means 3 is operating normally, but the function of the watchdog timer 2 is normal. It is not possible to check whether or not it is working. Therefore, another specific example of the central processing unit monitoring system according to the present invention provides a central processing unit monitoring system to which a function for monitoring the operation of the watchdog timer circuit 2 is added.

FIG. 5 is a block diagram for explaining another example of the monitor system for the central processing unit. That is, in the present specific example, the reset pulse generating means 11 provided in the watchdog timer 2 and the reset pulse input terminal portion 9 provided in the central processing unit 1 are connected in the middle of the wiring 51. The gate means 52 for inhibiting the reset pulse RP from being input to the reset pulse input terminal portion 9 is provided, and the gate means 52 is provided by the output of the reset inhibition output terminal portion 50 provided in the central processing unit 1. 52 is a central processing unit monitor system configured to be controlled.

Further, the gate means 52 is controlled by the output of the reset prohibition output terminal section 50 so that the reset pulse RP is not inputted to the reset pulse input terminal section 9 and then the pulse of the central processing unit 1 is outputted. It is configured to stop the means for generating the pulse P of a predetermined cycle output from the output terminal 8 to the watchdog timer 2.

After the function of the predetermined period pulse generating means is stopped, it is judged from the drive status of the alarm means 7 whether the operation of the watchdog timer circuit is normal or not. According to the system, It is also possible to simultaneously determine the operating status of the central processing unit monitor means. It is a thing.

The gate means 52 according to this example may be constituted by, for example, a PNP type transistor, the collector of which is the output terminal of the reset pulse generating means 11 provided in the watchdog timer 2 and the central processing unit. 1 is connected in the middle of the wiring 51 for connecting to the reset pulse input terminal portion 9 provided in No. 1 and the emitter portion thereof is connected to a predetermined power source.

The base of the transistor is connected to the reset inhibition signal output terminal section 50 provided in the central processing unit 1, and the transistor 52 is controlled by the reset inhibition signal. When the transistor 52 is turned on, the voltage of the reset input terminal section is fixed to the "H" level, so that the "L" level reset pulse output from the watchdog timer 2 is input to the reset input terminal section 9. You can prohibit being played.

In this example, when it is necessary to check the operating state of the watchdog timer 2,
First, the reset inhibit signal is output from the reset inhibit signal output terminal section 50 to turn on the transistor 52,
The voltage of the reset input terminal section 9 is fixed at "H" level to prohibit the reset pulse from the watchdog timer 2 from being input to the reset input terminal section 9.

After that, the output of the pulse P output from the pulse P output terminal section 8 is stopped. As a result, the watchdog timer 2 outputs the reset pulse RP after the lapse of a predetermined time because the pulse P has stopped, but the reset pulse RP is not supplied to the reset input terminal section 9 of the central processing unit 1. No input is made, so that the central processing unit 1 is not reset.

If such a state is continued for a while, if the watchdog timer 2 is in a normal state, the watchdog timer 2 outputs the reset pulse RP a plurality of times (for example, 10 times) as described above. Therefore, if the pulse-voltage converting means 5 is operating normally, a signal indicating that the central processing unit is in an abnormal state is output from the pulse-voltage converting means 5, and the alarm means driving means is activated. Whether the alarm means is activated or the signal is directly input to the alarm signal input terminal portion 53 of the central processing unit 1 and the information is judged by the central processing unit 1 itself to determine whether or not the operation of the watchdog timer 2 is normal. It is determined.

That is, in this embodiment, the operation of the central processing unit 1 is intentionally stopped once, and it is checked whether or not the watchdog timer 2 notifies the abnormality. is there. FIG. 6 shows a flowchart for operating such a monitor system. After the start, the reset prohibition signal is output from the reset prohibition signal output terminal section 50 in step (1), whereby the reset prohibition signal is output in step (2). The transistor 52 is turned on, and the voltage of the reset input terminal section 9 is fixed to the "H" level (step (3)).

Then, in step (4), the pulse P
The output of the pulse P output from the output terminal unit 8 is stopped. Thereafter, in step (5), it is judged whether or not the alarm means has been driven by the operator or the central processing unit 1 itself, and if YES, the function of the watchdog timer 2 becomes normal in step (6). If it is judged that the central processing unit 1 is operating, if NO, the process goes to step (7) to output the pulse P from the central processing unit 1 to restore the normal operation of the central processing unit 1.

As a result, in step (8), the watchdog timer 2 starts the monitor operation,
In step (9), it is judged again whether the alarm means 7 has been driven by the operator or the central processing unit 1 itself. If YES, the function of the watchdog timer 2 is abnormal in step (10). Judge that there was. If NO, the process proceeds to step (11) to judge that the function of the central processing unit monitor means 3 is abnormal.

[0049]

Since the monitor system of the central processing unit according to the present invention adopts the above-mentioned configuration, the central processing unit 1, the watchdog timer 2 and the central processing unit are always operated with a simple circuit configuration. Whether or not both the monitor means 3 are normally operating can be individually and accurately detected. If at least one of the functions fails, the state of the circuit is immediately notified. By stopping the operation or displaying a warning to the operator,
It is possible to obtain a monitor system for a central processing unit that can prevent accidents from occurring.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a principle and a specific example of a monitor circuit of a monitor system of a central processing unit according to the present invention.

FIG. 2 is a flow chart for explaining the operation of the monitor system of the central processing unit according to the present invention.

FIG. 3 is a flow chart for explaining an operation for checking the operation of the central processing unit monitor means in the central processing unit monitoring system according to the present invention.

FIG. 4 is a block diagram showing another configuration example of the central processing unit monitoring means used in the central processing unit monitoring system according to the present invention.

FIG. 5 is a block diagram showing another specific example of the monitor system of the central processing unit according to the present invention.

FIG. 6 is a flowchart illustrating an operation procedure in the specific example of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Central processing unit 2 ... Watchdog timer 3 ... Central processing unit monitoring means 4 ... Warning means 5 ... Pulse-voltage conversion means 6 ... Comparator 7 ... Warning means driving means 50 ... Reset prohibition pulse output terminal 52 ... Gate means 53 ... Warning Means drive signal input terminal

Claims (9)

[Claims] 1. A central processing unit, a watchdog timer connected to the central processing unit, a central unit for detecting whether or not the function of the central processing unit connected to the watchdog timer is operating normally. A monitor system comprising an arithmetic unit monitoring means and an alarm means connected to the central arithmetic unit monitoring means, wherein the central arithmetic unit has a predetermined cycle from the central arithmetic unit to the watchdog timer. A means for generating a pulse is provided, and in the watchdog timer, a reset pulse generating means is provided for generating a reset pulse to the central processing unit when a predetermined pulse from the central processing unit stops Further, the central processing unit monitoring means monitors the reset pulse output from the watchdog timer and resets the reset pulse. A function of the central processing unit to determine whether the function of the central processing unit is operating normally from the information obtained by the pulse. A central processing unit monitor system characterized by being driven in response to an output indicating an abnormality. 2. The central processing unit monitor means outputs a pulse-voltage converting means for generating a voltage corresponding to the number of reset pulses output from the watchdog timer during a predetermined period, and the pulse-voltage converting means outputs the voltage. A voltage comparing means for comparing a predetermined voltage with a predetermined reference voltage, and an alarm means driving means driven in response to an output from the voltage comparing means indicating that the function of the central processing unit is abnormal. The monitoring system for a central processing unit according to claim 1, characterized in that the monitoring system comprises: 3. The pulse-voltage converting means is further provided in the central processing unit so that a pseudo pulse corresponding to the reset pulse is supplied from a monitor terminal section. Item 2. A monitoring system for a central processing unit according to Item 2. 4. A monitoring system for a central processing unit according to claim 2, wherein the output of said alarm means driving means in said central processing unit monitoring means is fed back to said central processing unit. .. 5. The monitor system for a central processing unit according to claim 2, wherein the pulse-voltage converting means has a function of generating a voltage in response to a change in the frequency of the reset pulse. 6. The pulse-voltage conversion means is composed of a capacitor, and is configured to input the plurality of reset pulses to the capacitor and output the charging voltage thereof. The monitoring system of the central processing unit according to 2. 7. The reset pulse input terminal is provided with the reset pulse in the middle of a wiring connecting a reset pulse generating means provided in the watchdog timer and a reset pulse input terminal section provided in the central processing unit. In addition to providing gate means to prohibit input to the department,
2. The monitoring system for a central processing unit according to claim 1, wherein the gate means is controlled by an output of a reset prohibition output terminal section provided in the central processing unit. 8. The watchdog timer in the central processing unit after controlling the gate means by the output of the reset prohibition output terminal to prevent the reset pulse from being input to the reset pulse input terminal. 8. The monitoring system for the central processing unit according to claim 7, wherein the function of the predetermined period pulse generating means for the above is stopped. 9. The operating status of the watchdog timer circuit and the central processing unit monitoring means is determined from the driving status of the alarm means after the function of the predetermined period pulse generating means is stopped. Central processing unit monitoring system.