JPH09203751A - Monitoring circuit for positive-negative ac power source - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure that abnormal voltages can be detected even if the (+) and (-) side divided voltages of a positive-negative dc power source fluctuate likewise by providing an abnormality output when detecting that each of the (+) and (-) side divided voltages of a positive-negative dc power source has dropped to a predetermined level or less. SOLUTION: Voltage dividing circuits 11A, 11B comprise resistances R1 to R4 that divide the (+) and (-) side voltages of a positive-negative dc power source such as a ±15-voltage power source, each of the divided voltages VA, VB becoming 1.25V when ±15V becomes 13V. When it is 1.25V or less, voltage- detecting ICs 13A, 13B output H, and the secondary side output of each photocoupler 15A, 15B becomes H. This output is inverted by inverters 17A, 17B and input to an abnormal output OR circuit 19. Thus when the ±15-V source voltage is ±13V or more, the outputs of the ICs 13A, 13B becomes L while the output of the circuit 19 becomes H, so that no abnormality is detected. When either or both of the (+) and (-) sides of the source voltage become 13V or less, one or both of the outputs of the ICs 13A, 13B become H while the output of the circuit 19 becomes L, and an abnormal state is announced to the outside by means of light-emitting diodes, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monitoring circuit for a positive / negative DC power supply which detects an abnormality in the voltage of a ± 15V DC power supply or the like in a digital relay.

[0002]

2. Description of the Related Art A digital protective relay, as shown in FIG. 5, simultaneously samples and holds the instantaneous values of a plurality of system inputs such as voltage and current by a sample and hold circuit 1 and multiplexes the sampled and held analog values by a multiplexer 2. , The A / D converter 3 sequentially converts the digital value into a digital value, and the CPU 4 uses this sampling data to perform a protection relay operation.

In this digital protective relay, a ± 15 V DC power source 5 is used as the power source for the A / D converter 3.
In order to monitor this ± 15V DC voltage, this voltage is divided by the voltage dividing circuit 6 consisting of the resistors R _A and R _B to create a 3V monitoring input, which is input to the open channel of the multiplexer 2 and A / The digital value of the monitoring input converted by the D converter 3 is read by the CPU 4, and when it exceeds the control value, it is regarded as ± 15 V abnormality.

[0004]

In the above-mentioned ± 15V DC voltage monitoring circuit, 3V is generated and monitored by the voltage division of the resistors R _A and R _B , so ± 15V is unbalanced on the + side and the-side. If it fluctuates, 3V at the voltage dividing point fluctuates, so it is possible to detect abnormalities. However, if the + side voltage and the − side voltage similarly rise or fall, the voltage ratio does not change, so 3 V at the voltage dividing point. Results in almost no change, and the abnormal voltage cannot be detected.

The present invention has been made in view of the above problems of the prior art, and its object is to:
It is an object of the present invention to provide a monitoring circuit for a positive / negative DC power supply that can reliably detect a voltage abnormality even when the positive and negative voltages of the positive / negative DC power supply similarly change.

[0006]

To achieve the above object, a monitoring circuit for a positive / negative DC power supply according to the present invention divides the positive and negative DC power supplies into positive and negative voltages, respectively, and each divided voltage has a predetermined voltage. It comprises a + side voltage detection circuit and a − side voltage detection circuit that detect a voltage drop below a level, and a logic circuit that is connected to each voltage detection circuit and outputs an error when one or both voltage detection circuits detect a voltage drop. is there.

Alternatively, an abnormal output flip-flop, an abnormal output monomultivibrator for operating the abnormal output of the logic circuit to output the flip-flop, and an abnormal output of the logic circuit are activated. Recovery flip-flop for recovering the flip-flop, and an output lock for locking the outputs of the abnormal output and abnormal recovery mono-multivibrator respectively for a minute time from the rise of the circuit voltage or the recovery of the abnormal output of the logic circuit. It is provided with a circuit.

[0008]

Embodiments of the present invention will be described with reference to the drawings. 1 and 2 show the circuits of the front stage part and the rear stage part of the monitoring circuit.

Referring to FIG. 1, 11A and 11B are voltage dividing circuits consisting of resistors R _{1 to} R _{4 for} dividing the positive and negative side voltages of a positive and negative DC power source such as ± 15V power source, for example, ± 15V.
When the respective voltages become 13 V, the divided voltages V _A and V _B become 1.25 V. 13A and 13B are voltage detecting IC output is "H" when the divided voltage V _A and V _B becomes 1.25V or less, 15A and 15B IC 15a, at photocoupler connected to 15B, IC1
When the outputs of 3A and 13B are "H" respectively 2
The output on the secondary side becomes "H".

Reference numerals 17A and 17B denote inverters for inverting the output of the photocoupler, and 19 denotes inverters 17A and 17B.
It is an abnormal output logical sum circuit in which NOT is added to the input / output unit to which the output of B is input.

Referring to FIG. 2, reference numeral 21 is a voltage detecting IC 22.
Is used to detect an anomaly when the voltage Vcc rises and output a reset signal, 23 is a mono-vibrator for anomalous output, and pin 9 is connected to the OR circuit 19 (FIG. 1). Signal 2 again on pin 11 circuit 2
The reset signal from 1 is input. Reference numeral 26 is an abnormality recovery mono-multivibrator, and the signal from the circuit 19 (FIG. 1) is input to the pin 2 and the reset signal from the circuit 21 is input to the pin 3.

An output lock circuit 31 locks the outputs of the mono-multivibrators 23 and 26 for a certain period of time, for example, 100 nsec, in order to prevent malfunction due to noise. The input / output circuit receives the signal from the circuit 19 and the circuit voltage Vcc. An OR circuit 32 having a NOT in its part, and a delay circuit 33 for delaying its output by 100 nsec,
An inverter 34 that inverts the delayed signal, an AND circuit 35 that blocks the output of the monomultivibrator IC 23 when its output is "L", an inverter 36 that inverts the output of the inverter 34, and its output is "L". In this case, the AND circuit 37 blocks the output of the mono multivibrator 26.

Reference numeral 41 denotes an abnormal output flip-flop, which receives a signal obtained by inverting the signal from the AND circuit 35 by the inverter 38 at pin 1, and inputs the signal of the AND circuit 37 at pin 3. 42 is an inverter that inverts the signal from the flip-flop 41, 43 is an inverter that inverts the signal from the inverter 42, 46 is a photocoupler that outputs an error display signal when the output of the inverter 43 becomes "L". The relay 47 is turned on.
Is energized and the contact 47a is closed to turn on the external display 48.

Since it is constructed as described above, ± 15
When the V power supply voltage is normal at ± 13 V or more, the outputs of the voltage detection ICs 13A and 13B are “L”, the output of the OR circuit 19 is “H”, and no abnormality of ± 15 V is detected. In this case, the output of the OR circuit 32 is "H", the output of the inverter 34 is "L", and the output of the abnormal output mono multivibrator 23 is "H". Therefore, the output of the AND circuit 35 for generating an abnormal output is "L", the output of the flip-flop 41 is "H", the output of the inverter 43 is "H", and the photocoupler 46 is in the OFF state. Is not output.

Next, the operation when an abnormality is detected will be described with reference to FIG. 3a.

The symbols of the signals A to K in FIG.
It is a signal of each part attached to FIG.

If an abnormality occurs at time t ₀ and one or both of the +/− side voltages of the ± 15 V power supply voltage becomes 13 V or less, one or both outputs of the voltage detection ICs 13A and 13B are “H”. , The output of the OR circuit 19 becomes "L" as indicated by a signal in A of FIG. 3a.

As a result, the monomulti hanoi vibrator 2
The output E of 3 becomes "L" and is applied to one gate of the AND circuit 35. However, since the signal D of the other gate of this circuit 35 is "L", the output signal F is "L". There is.

On the other hand, the output B of the logical sum circuit 32 becomes "L" at the same time as the signal E becomes "L", but the input signal C of the inverter 34 is gradually lowered by the action of the delay circuit 33, and at time t ₁ . Then, the output D of the inverter 34 becomes "H" and is applied to one gate of the AND circuit 35.

When the output E of the monomultivibrator 23 is inverted to "H" at time t ₂ , the AND circuit 3
The output F of 5 becomes "L", the output of the inverter 38 becomes "L", the flip-flop 41 is cleared, and its output K
Becomes "L". Therefore, the output of the inverter 42 becomes "H", the output of the inverter 43 becomes "L", the photocoupler 46 is turned on, the relay 47 operates, and its contact 47 is generated.
Light-emitting diode 48 indicates that an abnormal state has occurred via a.
Notify the outside by such as.

FIG. 3B is a time chart showing a state in which the output is locked by the output lock circuit 31 and an abnormal signal is not output from the flip-flop 41 even if an erroneous abnormality is detected due to noise or the like. is there. Further, FIG. 4A is a time chart at the time of recovery after the occurrence of an abnormality.

At time t ₁₁ , the signals A and B are "L" at the time of abnormality.
Invert the "H" than the level, the signal C of Deirei circuit 33 rises with a time constant of CR, the inverter 34 at time t ₁₂ operates reached its threshold, the signal D is "L",
G becomes "H". On the other hand, Mono Multi Vibrator 2
6 starts operation by "H" change of the signal A, the "H" output I at time t _13. As a result, the outputs J and K of the AND circuit 37 and the flip-flop 41 respectively become "H", the output of the inverter 43 also becomes "H", the photocoupler 46 is turned off, and the relay 47 is deenergized.

FIG. 4 (b) shows a time chart at the time of erroneous recovery due to noise or the like, showing a state where no abnormal recovery output is generated.

Further, the power-on abnormality detecting circuit 21 is
Since the rise delay of the voltage Vcc at power-on is detected and the reset signal is output to the flip-flop IC41 for locking, the flip-flop IC41 does not malfunction due to power-on abnormality.

[0025]

Since the present invention is configured as described above, the following effects can be obtained.

(1) Even if the +/- side of the ± DC power supply voltage rises or falls similarly, the voltage abnormality can be detected.

(2) No malfunction occurs due to noise and delay in rising of the voltage Vcc.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first half of a ± DC power supply monitoring circuit according to an embodiment.

FIG. 2 is a circuit diagram showing the latter half of the same.

FIG. 3A and FIG. 3B are a time chart of abnormality detection and a time chart of when noise occurs.

4A and 4B are a time chart at the time of recovery from an abnormality and a time chart at the time of noise occurrence.

FIG. 5 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 11A, 11B ... Voltage dividing circuit 13A, 13B ... Voltage detection IC 23 ... Abnormal output mono multivibrator IC 26 ... Abnormality recovery mono multivibrator IC 31 ... Output lock circuit 41 ... Flip-flop IC

Claims (2)

[Claims] 1. A + side voltage and a − side voltage detection circuit for dividing the + side voltage and the − side voltage of a positive / negative DC power source, respectively, and detecting that each divided voltage has dropped below a predetermined level, and each voltage detection circuit. A logic circuit that is connected to the circuit and outputs an error when one or both voltage detection circuits detect a voltage drop;
A monitoring circuit for positive and negative DC power supplies, characterized in that 2. The abnormal output flip-flop, the abnormal output mono-multivibrator which operates by the abnormal output of the logic circuit to output the flip-flop, and the abnormal output of the logic circuit are eliminated. An abnormal recovery flip-flop that operates to recover the flip-flop and the outputs of the abnormal output and abnormal recovery mono-multivibrator are locked for a minute time after the rise of the circuit voltage or the recovery of the abnormal output of the logic circuit, respectively. An output lock circuit and a monitoring circuit for positive and negative DC power supplies.