JPH04156145A - Signal break detecting circuit for bipolar signal - Google Patents

Abstract

PURPOSE:To easily set a detection condition in accordance with the use by logically combining-level fixed and non-varied states of respective unipolar signals to generate the detection condition according with the use and synthetically discriminating a monitor result signal group to determine, whether a signal is broken or not. CONSTITUTION:A converting part 41 which converts a bipolar signal to three unipolar signals, namely, a positive-polarity component signal, a negative-polarity component signal, and a clock and a detection condition generating part 42 which logically combines level fixed and non-varied states of respective unipolar signals to generate the detection condition according with the use and outputs it as a signal group to be monitored are provided. The monitor result signal group of a latch group 43 which monitors the signal group to be monitored of the detection condition generating part 42 with a prescribed detection period and outputs the monitor result signal group is synthetically discriminated to determine whether the signal is broken or not, and the discrimination result is outputted. Consequently, all digital signals can be recognized with the low or high logical level. Thus, the detection condition is easily changed even if the detection condition is changed in accordance with a device on which this circuit is mounted.

Description

[Detailed Description of the Invention] [Summary] Regarding a bipolar signal signal disconnection detection circuit that can detect a "signal disconnection" of a bipolar signal received from a digital transmission path under various detection conditions, the detection conditions can be set according to the purpose of use. For the purpose of making it easier to investigate the cause of failure when a "signal disconnection" actually occurs, the bipolar signal is divided into three unipolar signals: a positive side component signal, a negative side component signal, and a clock. A conversion unit that performs conversion, a detection condition creation unit that logically combines states in which the level of each unipolar signal is fixed and does not move to create detection conditions according to the purpose of use and outputs them as a group of monitored signals; A latch group that monitors the monitored signal group of the creation unit at a predetermined detection cycle and outputs it as a monitoring result signal group, and a latch group that comprehensively evaluates the monitoring result signal group of the latch group to determine whether or not there is a signal disconnection. and a determination unit that outputs the result.

[Industrial Application Field 1] The present invention relates to a bipolar signal signal disconnection detection circuit that can detect a "signal disconnection" of a bipolar signal received from a digital transmission line under various detection conditions.

In current digital communication networks, as shown in FIG. 5, information is exchanged on the transmission path using bipolar signals SO. When the digital signal processing device 30 receives this bipolar signal SO, as a first step, the bipolar/unipolar conversion circuit 31 converts one bipolar signal SO into three unipolar signals consisting of positive data Sl, negative data S2, and clock S3. converted into a signal. Here, as shown in FIG. 6, the positive side data S1 is the positive potential side component of the bipolar signal SO, the negative side data S2 is the negative potential side component of the bipolar signal SO, and the clock S3 is the basic value extracted from the bipolar signal SO. It is a frequency component. These three separated unipolar signals are later logically processed in a logic circuit 32 represented by an LSI or TTL-IC, and are finally divided into two parts: the NRZ data S20 and the clock S3.
Condensed into books.

Considering the entire system from the standpoint of the logic circuit 32, if a failure, disconnection, etc. occurs before the input to the logic circuit 32 and it becomes impossible to receive a normal signal, some countermeasures should be taken. It becomes necessary. For this reason, a circuit is required that can constantly monitor the unipolar signals S1, S2, and S3, quickly detect signal interruption, and estimate the cause and location of the interruption.

The signal detection circuit according to the present invention satisfies such technical needs.

[Prior Art] An example of a signal disconnection detection circuit that has been widely used in the past is shown in FIG. In the figure, 21, 22, and 23 are D flip-flops, and a fixed voltage of +5■ is input to their data input terminals, and a delay element (approximately 1/4 bit of the digital input signal) is input to their reset input terminal RST. The timer pulse S4 is inputted as a control signal S9 via a delay of . Further, positive II+data Sl is input to the clock input terminal CLK of the flip-flop 21, negative data S2 is input to the clock input terminal CLK of the flip-flop 22, and clock S3 is input to the clock CLK of the flip-flop 23.

The output signal from the output terminal Q of each D flip-flop 21 to 23 is input to the NAND circuit 25, and the NAND circuit 2
The output signal of 5 is input to the data input terminal of the D flip-flop 26. A timer pulse S4 is input to the clock terminal CLK of this D flip-flop 26.

Here, positive side data Sl, negative side data S2, clock S3
is a unipolar signal separated into three parts, with the same frequency C
bit transmission rate). The timer pulse S4 is a normal wave (constant periodic wave) pulse of positive polarity for setting the detection period, and is generated by an oscillator inside the device.

This signal disconnection detection circuit has the following (at, (bl,
The operation is performed using the three cases (c) as detection conditions.

fa) If the positive data S1 no longer exists fb)
When the rising edge of the negative side data $2 disappears [c) When the rising edge of the clock S3 becomes weak, the input signal S1. S
2. If a failure or disconnection occurs in any of S3, the input signal will change to the power supply side potential (“H”’=+
5V) or ground! 111 potential (L"' = ov) and does not move. This is the timer pulse S4.
If it continues throughout the detection period set by , it is determined that the signal is disconnected.

In other words, the input signal S1. When the rising edge of either S2 or S3 disappears, one of the flip-flops 21 to 23 that corresponds to that input signal receives data +5V (=
Therefore, the flip-flop will maintain -L'' as an output signal during the detection period from when it is reset by timer pulse S9 until the next reset. The output of this NAND circuit 25 is taken into the D flip-flop 26 at the timing of the timer pulse S9, and the output signal of the flip-flop 26 is detected as the final "signal disconnection" detection result. It becomes a down detection signal S15 of (-) indicating the detected pressure.

[Means for Solving the Three Problems 1] The above-mentioned signal disconnection detection circuit is logically simple and clear and is therefore widely used. However, it can be said that this circuit actually makes a serious mistake in its recognition of processing digital signals. This is because in general logic circuits, for positive data S1 and negative data S2, “
Considering the level of L″′ or °゛H″′, the clock S
This is because the above-mentioned signal disconnection detection circuit considers only the presence or absence of a rising edge as the detection condition, whereas the above-mentioned signal disconnection detection circuit considers the presence or absence of a rising edge as a problem for No. 3.

In other words, under the above-mentioned detection conditions (a) and (bl), it can be said that the recognition of the positive side data S1 and the negative side data 82 is poor.

As a result, as shown in FIG. 8, for example, when the timer pulse S8 is reset, if the negative data S2 is "I(-"), there is a possibility that the conventional circuit will erroneously detect "signal disconnection". be.

In addition, other detection strips (recombining with raw material, e.g. "L"
When changing the detection conditions to detect only when the signal is fixed as ``signal disconnection'', the modification results in a cumbersome circuit structure, so it is a circuit with very limited application when setting the detection conditions It becomes.

Furthermore, when a "signal cut" actually occurs, it is difficult to diagnose what kind of "signal cut" the "signal cut" is, and it is difficult to infer the cause or location from the detection results. becomes. For example, it is difficult to determine whether a failure is in the transmission path or a bipolar/unipolar conversion circuit, or whether it is a ground fault or a short-circuit failure on the power supply side.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to facilitate the setting of detection conditions according to the purpose of use, and to identify the cause of failure when a "signal interruption" actually occurs. It is an object of the present invention to provide a signal disconnection detection circuit for bipolar signals that is easy to track.

[Means to solve the problem 1 FIG. 1 is a diagram explaining the principle of the present invention.

The signal disconnection detection circuit for a bipolar signal according to the present invention includes a conversion unit 41 that converts a bipolar signal into three unipolar signals, a positive side component signal, a negative side component signal, and a clock, as one state a, and a converter 41 for converting each unipolar signal into three unipolar signals: a detection condition creation unit 42 that logically combines states in which the levels of are fixed and does not move to create detection conditions according to the purpose of use and outputs them as a group of monitored signals; and a group of monitored signals of the detection condition creation unit 42. a latch group 43 that monitors the signals at a predetermined detection cycle and outputs them as a group of monitoring result signals; and a determination section that comprehensively judges the group of monitoring result signals of the latch group, determines whether or not there is a signal disconnection, and outputs the result as a judgment result. 44.

Further, the signal disconnection detection circuit for bipolar signals according to the present invention includes:
Another configuration includes a converter that converts a bipolar signal into three unipolar signals: a positive polarity side component signal, a negative polarity side component signal, and a clock; a first flip-flop that retimes the positive polarity II+ component signal using a clock; a second flip-flop for retiming the negative side component signal; and a group of latches for monitoring the output signals and inverted output signals of the first and second flip-flops, each latch being reset periodically and The input signal is configured to be set when a condition occurs, and the determination section that determines whether or not a signal disconnection occurs based on a group of output signals from a group of latches is configured to have different widths.

Further, the signal disconnection detection circuit for bipolar signals according to the present invention includes:
Further, as another form, in the above-mentioned signal disconnection detection circuit,
It further includes a logic operation section that performs a logic operation on an arbitrary combination of the output signal and the inverted output signal of the first and second flip-flops, and outputs the output signal of this logic operation section to a subsequent latch group. configured.

[Operation] According to each of the above embodiments, all digital signals can be recognized at the logic level of "L-" or "H". To recognize a rising or falling edge, you can differentiate the change in the digital signal (No. 3). In other words, the characteristics of the digital signal are understood from the most basic factors. Even if the detection conditions for detecting a signal are changed, it is easy to change the detection conditions due to the circuit structure, so it is easy to deal with it.Furthermore, when a "signal interruption" occurs, the Since the occurrence status of "" is output, it becomes easier to analyze the cause and occurrence location to some extent.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

A signal disconnection detection circuit for bipolar signals as an embodiment of the present invention is shown in FIG. In Figure 2, l and 2 are D
The positive side data S1 is input to the data input terminal of the D flip-flop 1, and the negative side data S2 is input to the data input terminal of the D flip-flop 2. Further, the clock S3 is input to each clock input terminal CLK of the D flip-flop 1.2. Here, the positive data S1, the negative data S2, and the clock S3 are unipolar signals obtained by dividing the bipolar signal SO into three parts, and have the same frequency (bit transmission rate). Further, the timer pulse S4 is a positive-polarity, standing wave (constant periodic wave) pulse for setting the detection period, and is generated by an oscillator inside the device.

3 to 6 are latch circuits, each with two N
Consists of an OR circuit. That is, this latch circuit has an input terminal to which a set signal is input and an input terminal ■ to which a reset signal is input, and the input terminal ■ is connected to the NOR circuit G1.
The input terminal ■ is connected to one input terminal of the NOR circuit G2, and the output signal of the NOR circuit G2 is input to the other input terminal of the NOR circuit G1.
The output signal of the NOR circuit G1 is configured to be fed back to the other input terminal of the NOR circuit G2.

The latch circuit 3 has a D flip-flop l at its input terminal.
The latch circuit 4 receives the inverted output signal S6 (=*Q) of the D flip-flop 1 at its input terminal I, and the latch circuit 5 receives the output signal S5 (=Q) of the D flip-flop at its input terminal I. output signal S7 (=Q
) is input manually, and the inverted output signal S8 (=*Q) of the D flip-flop 2 is input to the input terminal I of the latch circuit 6. A timer pulse S9 that has passed through the delay element 7 (delayed by about 1/4 bit of the digital input signal) is inputted as a reset signal to the input terminals (2) of each of the latch circuits 3 to 6, respectively.

Each of the latch circuits 3 to 6 sets its output signal to a reset state (“H”) by receiving a reset signal at the input terminal (2), and when the input signal input to the input terminal is “H” or ”, the output signal is fixed at the set state (“L”) until the next reset.

Output signal of each latch circuit 3 to 6 SIO-3L3 NO
Input to the R circuit 8 and monitor signals S16 to S1
9 and is led to the monitor terminal. The output signal S14 of the NOR circuit 8 is input to the data input terminal of the D flip-flop 9. A timer pulse S4 is input to the clock input terminal CLK of this D flip-flop 9, and a down detection signal S15 is output from its inverted output terminal *Q.

The operation of the circuit of this embodiment will be explained below. First, the overall operation of the example circuit will be described.

If a failure, disconnection, etc. occurs in any of the input signals S1, S2, and S3, the input signal will be either at the power supply side potential (“H”' = +5V) or at the ground side potential ('L') depending on the electrical characteristics.
"' = OV) and does not move. If this state continues throughout the detection period set by the timer pulse, it is determined that the signal is off. In this example circuit, the following five cases fj) to fn) are used as "signal disconnection J detection conditions. In other words, (j) positive side data S1 is fixed at "L" and does not move. If not (k + positive shout data Sl is fixed at "H" and does not move (1) Negative side data S2 is fixed at "1.,," and does not move (a) Negative side data S2 is °H The case where it is fixed at ``'' and does not move fn) This is a case where the rising edge of the clock S3 disappears.

The input positive side data Sl and negative side data S2 are retimed by the clock S3 in D flip-flops 1 and 2, respectively, and these D flip-flops 1 and 2 are retimed by the clock S3.
From the output side, timed output signals 85 to S8 are obtained. These output signals 85-S8 are input to input terminals (2) of latch circuits 3-6, respectively.

Output signals S10, S of these latch circuits 3.4.5.6
11. S12 and S13 are detection conditions fj) and (
kill), (ntl. That is, the output signal SIO corresponds to the output signal SIO when the positive data S1 is fixed to "L"', and the output signal Sll corresponds to The negative side data S2 of the signal SL2 is °°L''
and when the negative side data S2 is fixed at "H", the output signal S13 becomes "H"'. When each detection condition is not applicable, each output signal SIO
~813 is "L"'. When detection condition (n) occurs, D flip-flop 1.2 loses clock power and the output stops moving, so in the end, detection condition fj
l, fk+, (11, (+ml), and the occurrence of detection condition (n) can be indirectly detected.

Each of the latch circuits 3 to 6 is reset at regular intervals by a timer pulse S9, thereby repeatedly determining the presence or absence of the above detection condition at every regular detection cycle.

The output signals SIO to S13 of these latch circuits 3 to 6 are N
The OR circuit 8 performs a logical sum, and the NOR circuit 8 outputs a determination result S14. Therefore, when it is determined that there is a "signal interruption", the determination result S14 becomes "L". This is the down detection signal SI5 which is the detection result of the disconnection.

The output signals S10-S13 of the latch circuits 3-6 are also outputted to monitor terminals as monitor signals 816-S19.

By checking these monitor signals S16 to S519,
It is possible to infer the location and cause of signal interruption.

Here, the timer pulse S4 can be set to any period according to the user's intention. Based on the period of this timer pulse S4, the determination result S14 is determined in the D flip-flop 9.
is extracted as the down detection signal S15, and then the four latch circuits 3 to 6 are reset to the initial state by the control signal S9. Since the down detection signal S15 and the control signal S9 require a slight time difference in order to operate stably, a delay element 7 is provided.

A more detailed operation sequence of this embodiment circuit will be explained below with reference to FIG. Here, FIG. 3 is a time chart of the signals of each part of the circuit of the embodiment, and shows a case where a failure corresponding to the detection condition im) occurs as a "signal disconnection".

Now, when timer pulse S4 is input at time tl,
The output signals SIO to S13 of the latch circuits 3 to 6 are set to ``H'' only in the stages where the detection condition has occurred, and are reset to ``L'' in the stages that do not correspond to the detection condition from the beginning.

Then, when it is reset to "L"', it remains "L" until the next timer pulse S4 is input.

At time tl in FIG. 3, the positive...11 data Sl and the negative data S2 are at °L-, so at this point the detection condition is
(jl and (1) are generated, so the output signal S10
．． SI2 becomes "H"', and other output signals S11.31
3 is assumed to not meet the detection conditions from the beginning and is set as 'L'''.
becomes.

Next, when the positive data S1 changes to °H''' at time t2, the detection condition fjl no longer applies, so the output signal S
IO changes to "L" and is fixed there until the next reset. Similarly, when the negative data S2 changes to "H"' at time t3, the detection condition (1) is no longer met, so the output signal S12 changes to "L" and is fixed there until the next reset.

In this way, if the input signals S1, $2, and S3 are normal,
The output signals 85 to S8 of the D flip-flop 1.2 are ' within the detection period set by the timer pulse S4.
Since L'' and H''' are alternately repeated, all of the output signals SlO to S13 of the latch circuits 3 to 6 become ``L'' by the time the next timer pulse S4 is input manually.

When the output signals SIO to S13 all become L''' in this way, the determination result SI4 of the NOR circuit 8 becomes "H", and therefore, when the next timer pulse S4 is manually input at time Sl t 4, the determination result 514 ( ="H") is taken into the D flip-flop 9, and thereafter its inverted output terminal *Q
The down detection signal S15, which is the final “signal disconnection” detection result extracted from
It becomes -L-, which indicates "no signal interruption", until it is manually operated.

On the other hand, it is assumed that the negative side data S2 becomes abnormal due to the signal cut-off and is fixed at "H".
When the timer pulse S4 is inputted, the detection condition (
nt) occurs, and therefore, the output signal S8 of the D flip-flop 2 corresponding to the detection condition +ff1) remains "L"' and does not move, so the output signal S13 of the latch circuit 6 that inputs it becomes "H". It remains set to ″′.

If this "signal-off" state continues without being recovered by the time the next timer pulse S4 is input at time t5, the output signal 313 remains at ``H'' at time t5, so the NOR circuit 8 The determination result S14 is "L", and therefore the down detection signal S15 from the flip-flop 8 becomes "H"' after time t5, indicating that the occurrence of a "signal cut" has been detected.

At this time, if you observe the status of monitor signals S16 to S19, only monitor signal S19 is 'H'' and an abnormality has occurred, so it can be seen that a "signal disconnection" that corresponds to the detection condition (+ml) has occurred. , thereby making it possible to estimate the location and cause of the failure.

Thereafter, if the input signal returns to the normal state from the "signal cut", the down detection signal S15, which is the detection result, will follow it.

In the case of such an embodiment circuit, even if the negative side data S2 is 'H' when reset is applied by the timer pulse S4 as shown in FIG. There will be no more trouble.

Various modifications are possible in implementing the invention. For example, the detection conditions for "signal disconnection" are not limited to the detection conditions fjl to (n) of the above-described embodiments. For example, if you want to change the detection conditions depending on the purpose of use, add simple logic to any combination of the output signals 85 to S8 of the example circuit described above, and then add the latch circuit of the necessary stage. You can enter each of them. Furthermore, if it is desired to use rise and fall as detection conditions, these signals may be passed through a differentiating circuit.

Figure 4 shows the following four detection conditions (p) to (sl).
Another embodiment of the present invention is shown in which the circuit shown in FIG. That is, fP) When the positive side data S1 is fixed at L'' and does not move (q) When the negative side data S2 is fixed at -L'' and does not move fr) When the positive side data 81 and the negative side data S2 or both “H”
This is the case when the rising edge of the clock S3 becomes zero (fs).

The difference between this embodiment circuit and the embodiment circuit shown in FIG. 2 is as follows.
Each of the inverted output signals S6 and S8 of the flip-flop 1.2 is inputted to the input terminal ■ of the latch circuit 4 via the OR circuit IO, and thereby the detection condition (rl) is determined in the latch circuit 4. Circuit 6 is omitted. With this configuration, the above-mentioned detection conditions FIG+, fq)
, (one signal is disconnected when rL(s) occurs).

[Effects of the Invention] As explained above, according to the present invention, the detection conditions can be easily set for various different detection conditions by the device, and almost all "signal interruptions" that occur can be detected. This makes it possible to perform detection that is appropriate for the purpose of use, reduces the risk of false detection, and makes it easier to determine the cause of the failure when a "signal interruption" actually occurs.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a block diagram showing a signal disconnection detection circuit for a bipolar signal as an embodiment of the present invention, and FIG. 3 is a time chart of signals of each part of the embodiment circuit. FIG. 4 is a block diagram showing another embodiment of the present invention, FIG. 5 is a block diagram for explaining a digital signal processing device that handles bipolar signals, and FIG. 6 is a block diagram showing the signals of each part of the device shown in FIG. Time Chart FIG. 7 is a block diagram showing a conventional example of a signal disconnection detection circuit, and FIG. 8 is a time chart illustrating an erroneous detection pattern in the conventional circuit. In the figure, 1.2.9.21-23.26...D flip-flops 3-6...-Latch circuit 7.24...Delay element 8.1l-NOR circuit 10--OR circuit 25-・-NAND circuit

Claims (1)

[Claims] 1. A conversion unit that converts a bipolar signal into three unipolar signals: a positive side component signal, a negative side component signal, and a clock.
41), and a detection condition creation unit (41) that logically combines the states in which the levels of the respective unipolar signals are fixed and does not move, creates detection conditions according to the purpose of use, and outputs them as a group of monitored signals.
2), a latch group (43) that monitors the monitored signal group of the detection condition creation unit (42) at a predetermined detection cycle and outputs it as a monitoring result signal group; and a monitoring result signal of the latch group (43). A signal disconnection detection circuit for bipolar signals, comprising a determination unit (44) that comprehensively evaluates the group, determines the presence or absence of signal disconnection, and outputs the result as a determination result. 2. A conversion unit that converts a bipolar signal into three unipolar signals: a positive component signal, a negative component signal, and a clock; a first flip-flop that retimes the positive component signal using the clock; and a first flip-flop that retimes the positive component signal using the clock; a second flip-flop that retimes the negative side component signal; and a group of latches that respectively monitor the output signal and the inverted output signal of the first and second flip-flops, each latch being reset periodically. a bipolar signal comprising: a signal that is configured to be set when a condition occurs in the input signal; and a determination unit that determines whether or not a signal disconnection occurs based on a group of output signals from the group of latches. disconnection detection circuit. 3. It further includes a logic operation section that performs a logic operation on any combination of the output signal and the inverted output signal of the first and second flip-flops, and inputs the output signal of this logic operation section to the subsequent latch group. 3. The bipolar signal disconnection detection circuit according to claim 2, wherein the bipolar signal disconnection detection circuit is configured to perform the following.