JPH0629964A - Frame pulse detection circuit - Google Patents

Abstract

PURPOSE:To detect accurately a trailing edge of a frame pulse by taking extension and contraction of a NT reception pulse width caused by wiring structure into account with respect to the frame pulse detection circuit detecting the trailing edge of the frame pulse required to recover a clock signal from the reception data in an ISDN basic access network terminator. CONSTITUTION:A violation pulse detection circuit 2 which receives positive and negative unipolar signals converted by a bipolar/unipolar conversion circuit 1 to detect a violation pulse counts a pulse width of a unipolar signal based on a multi-point sampling clock, has lots of pulse detection threshold levels and compares the count with each threshold level to detect the pulse based on a received switching signal S6 and a 2nd mask signal outputted from a 2nd mask generating circuit 4B by taking the expansion and compression of the width of the received pulse into account thereby detecting a violation pulse then detecting accurately the trailing edge of the violation pulse.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame pulse detecting circuit for detecting a falling edge of a frame pulse required for clock recovery from received data in an ISDN basic access network terminal device.

[0002]

2. Description of the Related Art FIG. 4 is based on a frame pulse falling edge detection method for an ISDN basic access interface published in, for example, "ISDN I Series International Standard and Its Technology" (April 1, 1988: Telecommunications Association). 1 is a circuit diagram, in which 1 is a bipolar unipolar conversion circuit for converting an input bipolar signal into a positive and negative unipolar signal, and 2 is a multi-point sampling clock for identifying the presence or absence of a pulse, A positive and negative violation pulse detection circuit for detecting the falling edges of the positive and negative unipolar signals, 3 is a switching circuit for switching the detection edges, 4
Is a mask generation circuit for generating a mask having a predetermined bit width from the determined falling edge of the frame pulse, and 5 is a 2-input AN
D gate, 6 is a toggle flip-flop that toggles the output signal by the output of the AND gate.

FIG. 5 shows a detailed configuration of the above-mentioned violation pulse detection circuit 2. In FIG.
1A and 21B are positive and negative pulse width counters, 22
A and 22B are first numerical comparison circuits having a first threshold level, 23A and 23B are second numerical comparison circuits having a second threshold level, and 27A and 27B are positive and negative violation detection circuits. .

Next, the operation will be described. First, FIG.
Shows the frame structure of the ISDN basic access interface. For simplicity, B1, B2 and D channels are all set to "1". In the frame received by the network terminating device, a frame pulse (frame bit indicating the beginning of the frame; hereinafter referred to as F pulse) and an auxiliary frame pulse (auxiliary frame bit, optionally Q bit; hereinafter referred to as FA pulse) The distinction uses code violation (the pulse exists in the same polarity as the previous pulse). Since each channel of B1, B2, and D in the frame is all "1", the F pulse causes a violation with the DC balanced bit (hereinafter, referred to as L pulse) located immediately before the same pole. Also, 1 after the F pulse
There is a rule to violate another pole within 3 bits. In the figure, L and FA are violating. Furthermore, the positive and negative poles must be erroneously connected to operate normally.

The operation according to the configuration of FIG. 4 described above will be described with reference to FIG. 6. In FIG. 4, when the bipolar signal input to the bipolar unipolar conversion circuit 1 has the wrong polarity, the violation pulse is input. The positive and negative violating pulse falling edges S2a and S2b output from the detection circuit 2 are output by the switching circuit 3 as erroneous discrimination frame pulse falling edges S3a. However, the mask generation circuit 4 uses the mask S having a width of 13 bits from the falling edge of the erroneously judged frame pulse.
4 is generated, the phase is compared by the FA pulse falling edge S3b for misjudgment and the AND gate 5, and after the F pulse, 1
Violation detection within 3 bits is performed. When a violation other than 13 bits is detected, the output S6 of the toggle flip-flop 6 is inverted based on the output S5 of the AND gate 5 to switch the positive and negative violating pulse falling edges S2a and S2b to cause a normal frame pulse rising. The falling edge S3a is output.

The operation of the violation pulse detection circuit 2 having the configuration shown in FIG. 5 will be described with reference to FIGS. 7 and 8. To the positive and negative pulse input terminals, the bipolar unipolar converted positive and negative pulses S1a and S1b from the receiver are input. The pulse width counter 21
When the count value exceeds the threshold level set in the first and second numerical comparison circuits 22A and 22B, 23A and 23B, the positive and negative pulse detection signals S22a and S22b, and It outputs S22a and S22b. This is the detection in the case of one pulse and the case of two consecutive pulses. By detecting these pulses, the falling edges S2a and S2b of the positive and negative electrode violations are detected.
Are detected separately.

[0007]

Since the conventional frame pulse detection circuit has the circuit configuration as described above, a short-distance passive bus is applied among the wiring configurations set by the basic access interface and a plurality of circuits are simultaneously operated. When a terminal is connected, pulse width expansion and compression occur in any bit of the NT received pulse. That is, when a plurality of terminals connected to the bus send data at the same time, the 1-bit duty of the received data changes due to the data delay between the terminals. At that time, the frame pulse is erroneously detected. In such a case on the first page, a 2-bit pulse is erroneously recognized as a continuous violation despite the 1-bit width pulse, and the violation detection circuit malfunctions. However, there is a problem in that the DPLL (digital phase locked oscillator) connected in the subsequent stage is erroneously operated. In addition, JP-A-63-203031 and JP-A-60-
Japanese Patent Laid-Open No. -144046 discloses a frame pulse detection technique.
There is no disclosure of a detection technique of a violation pulse in consideration of expansion and compression of T reception pulse width.

The present invention has been made to solve the above problems, and can accurately detect the falling edge of the frame pulse in consideration of the expansion and compression of the NT reception pulse width caused by the wiring configuration. An object is to provide a frame pulse detection circuit.

[0009]

In order to achieve the above object, a frame pulse detection circuit according to the present invention comprises a bipolar unipolar conversion circuit for converting a bipolar signal into positive and negative unipolar signals, and a positive electrode by multipoint sampling. And counting the pulse width of the unipolar signal of the negative polarity, and having a plurality of thresholds for pulse detection, inputting a switching signal in consideration of expansion and compression of the received pulse width, and a violation pulse based on the second mask signal. A violation pulse detection circuit that detects the falling edge of the switching violation pulse, a switching circuit that switches the positive and negative detection edges, and a first mask signal with a 13-bit width from the determined frame pulse falling edge. The first mask generation circuit and the determined frame pulse falling edge A second mask generation circuit for generating a second mask signal having a width of 15 bits from the pulse generator, a phase of the violation pulse having a pole opposite to the frame pulse, and the mask signal generated by the first mask generation circuit. And a toggle flip-flop that toggles according to the output of the AND gate and sends out a switching signal.

[0010]

The frame pulse detection circuit according to the present invention is configured to increase the number of pulse detection thresholds in the violation pulse detection circuit in consideration of the expansion and compression of the pulse width of the received pulse, thereby increasing the accuracy of the violation pulse. The pulse is switched, and the frame pulse falling edge is detected.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1 in which the same parts as those in FIG. 4 are denoted by the same reference numerals, the mask generation circuit is composed of first and second mask generation circuits 4A and 4B, and the first mask generation circuit 4A judges the frame pulse. A 13-bit width (192 KHz) mask signal is generated from the falling edge, and the second mask generation circuit 4B similarly generates a 15-bit width mask signal.

Further, the violation pulse detection circuit 2
As shown in FIG. 2, which will be described later, in consideration of the expansion and compression of the NT reception pulse width caused by the wiring configuration, there are two to three types of numerical comparison circuits for pulse detection included in the conventional violation pulse detection circuit. By appropriately increasing the number of bits to 1 bit, the data can be properly recognized with respect to the change of the duty of 1 bit, and the frame frame falling edge can be accurately detected.

Next, the operation of this embodiment will be described with reference to the timing chart of the output of each section shown in FIG. The NT reception frame input from the bipolar signal input terminal is output by the bipolar unipolar conversion circuit 1 as positive and negative unipolar signals S1a and S1b.
The violation pulse detection circuit 2 performs pulse recognition based on the multipoint sampling clock to detect the violation occurring at the positive and negative electrodes and outputs the falling edges S2a and S2b of the violation pulse. By the switching circuit 3, the frame pulse falling edge S
3a and the violating pulse falling edge S3b of another pole are selected. First mask generation circuit 4A
Generates a mask S4A having a 13-bit width from the frame pulse falling edge S3a, compares the phase with the violation pulse falling edge S3b detected at the pole different from the frame pulse by the 2AND gate 5, and confirms that the violation phase is When the frame rule is violated, the toggle flip-flop 6 is triggered and the switching circuit 3 is switched by the switching signal S6. The second mask generation circuit 4B generates a mask S4b having a 15-bit width from the frame pulse falling edge S3a and sends it to the violation pulse detection circuit 2 at the same time as the switching signal S6.

Here, as shown in FIG. 2, the above-mentioned violation pulse detection circuit 2 has positive and negative pulse S.
1a and S1b are counted by the pulse width counters 21A and 21B, and the first numerical comparison circuits 22A and 22B, the second numerical comparison circuits 23A and 23B, and the third numerical comparison circuits 24A and 2B.
4B, the first pulse detection signals S22a and S22b, the second pulse detection signals S23a and S23b, and the third pulse detection signal S24 while comparing the count value with each threshold.
a and S24b are output.

At this time, the second numerical comparison circuits 23A, 23
B and the third numerical comparison circuits 24A and 24B are positive and negative control signals S25a generated by the control circuit 25 based on the input of the first switching signal S6 and the second switching signal S4b generated from the falling edge of the frame pulse. , S26a, one of which is selected by the selectors 26A and 26B which perform selection operation.

From the above, the first numerical comparison circuits 22A, 2
Detection of one pulse by 2B and selectors 26A and 26B
The violence detection by the violence detection circuits 27A and 27B is performed by the continuous detection of two pulses selected in. For each pulse detection, as shown in FIG. 3, the thresholds set in each numerical comparison circuit are, for example, 1.7 μS for the first threshold, 9.3 μS for the second threshold, and 7. 3 for the third threshold. 2μ
It is set to S. Further, regarding the control signals S25a and S25b of the second threshold and the third threshold, for the same polarity as the detected frame pulse, there is no 2 consecutive bits in the 15-bit width from the frame pulse trailing due to the frame structure. , And the third threshold is selected so as to cope with frame pulse misrecognition thereafter. For the other pole than the frame pulse,
There is no violation pulse due to pulse width compression, so the second threshold is always selected.

By the above operation, the falling edge of the frame pulse is accurately detected without erroneously detecting the violation pulse.

In the above embodiment, the detection of the frame pulse falling edge necessary for the reproduction of the received clock with reference to the frame pulse of the ISDN basic access network terminating device has been described. You may change it.

[0019]

As described above, according to the present invention, it is possible to accurately set the violation pulse by setting and increasing many kinds of pulse detection thresholds in consideration of the expansion and compression of the NT reception pulse width caused by the wiring configuration. And the frame pulse falling edge detection is performed, so it can be applied regardless of the wiring configuration of the ISDN basic access interface.
This has the effect of accurately detecting the falling edge of the frame bit.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a frame pulse detection circuit according to an embodiment of the present invention.

FIG. 2 is an internal configuration diagram of a violation pulse detection circuit 2 in FIG.

FIG. 3 is a timing chart illustrating the operation of FIGS. 1 and 2.

FIG. 4 is a circuit diagram of a conventional frame pulse detection circuit.

5 is an internal configuration diagram of the violation pulse detection circuit 2 of FIG.

FIG. 6 is a timing chart illustrating the operation of FIG.

FIG. 7 is a timing chart illustrating the operation of FIG.

FIG. 8 is a timing chart explaining the operation of FIG. 5 in comparison with FIG. 7.

[Explanation of symbols]

 1 Bipolar Unipolar Conversion Circuit 2 Violation Pulse Detection Circuit 3 Switching Circuit 4A First Mask Generation Circuit 4B Second Mask Generation Circuit 5 2 Input AND Gate 6 Toggle Flip Flop 21A First Numerical Comparison Circuit 22A First Numerical Comparison Circuit 22B First numerical comparison circuit 23A Second numerical comparison circuit 23B Second numerical comparison circuit 24A Third numerical comparison circuit 24B Third numerical comparison circuit

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[Procedure amendment]

[Submission date] August 28, 1991

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

FIG. 5 shows a detailed configuration of the above-mentioned violation pulse detection circuit 2. In FIG.
1A and 21B are positive and negative pulse width counters, 22
A and 23A are first numerical comparison circuits having a first threshold level, 22B and 23B are second numerical comparison circuits having a second threshold level, and 27A and 27B are positive and negative violation detection circuits. .

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

The operation of the violation pulse detection circuit 2 having the configuration shown in FIG. 5 will be described with reference to FIGS. 7 and 8. To the positive and negative pulse input terminals, the bipolar unipolar converted positive and negative pulses S1a and S1b from the receiver are input. The pulse width counter 21
When the count value exceeds the threshold level set in the first and second numerical comparison circuits 22A and 22B, 23A and 23B, the positive and negative pulse detection signals S22a and S23a, and Output S22b and S23b . This is the detection in the case of one pulse and the case of two consecutive pulses. By detecting these pulses, the falling edges S2a and S2b of the positive and negative electrode violations are detected.
Are detected separately.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

Next, the operation of this embodiment will be described with reference to the timing chart of the output of each section shown in FIG. The NT reception frame input from the bipolar signal input terminal is output by the bipolar unipolar conversion circuit 1 as positive and negative unipolar signals S1a and S1b.
The violation pulse detection circuit 2 performs pulse recognition based on the multipoint sampling clock to detect the violation occurring at the positive and negative electrodes and outputs the falling edges S2a and S2b of the violation pulse. By the switching circuit 3, the frame pulse falling edge S
3a and the violating pulse falling edge S3b of another pole are selected. First mask generation circuit 4A
Generates a mask S4a having a 13-bit width from the frame pulse falling edge S3a, compares the phase with a violation pulse falling edge S3b detected at a pole different from the frame pulse with a 2-input AND gate 5, and When the phase violates the rule of the frame, the toggle flip-flop 6 is triggered and the switching circuit 3 is switched by the switching signal S6. The second mask generation circuit 4B generates a mask S4b having a 15-bit width from the frame pulse falling edge S3a and sends it to the violation pulse detection circuit 2 at the same time as the switching signal S6.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0015

[Correction method] Change

[Correction content]

At this time, the second numerical comparison circuits 23A, 23
B and the third numerical comparison circuits 24A and 24B are positive and negative control signals S25a generated by the control circuit 25 based on the input of the first switching signal S6 and the second switching signal S4b generated from the falling edge of the frame pulse. , S25a , one of which is selected by the selectors 26A and 26B which perform a selection operation.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] Explanation of code

[Correction method] Change

[Correction content]

[Description of Symbols] 1 bipolar unipolar conversion circuit 2 violation pulse detection circuit 3 switching circuit 4A first mask generation circuit 4B second mask generation circuit 5 2-input AND gate 6 toggle flip-flop 21A pulse width counter 21B pulse width counter 22A 1st numerical comparison circuit 22B 1st numerical comparison circuit 23A 2nd numerical comparison circuit 23B 2nd numerical comparison circuit 24A 3rd numerical comparison circuit 24B 3rd numerical comparison circuit

Claims (1)

[Claims] 1. A bipolar unipolar conversion circuit for converting a bipolar signal into positive and negative unipolar signals,
The pulse widths of the positive and negative unipolar signals are counted by multipoint sampling, and a switching signal that is input in consideration of expansion and compression of the reception pulse width that has multiple pulse detection thresholds and a second mask signal Based on the violence pulse detection circuit that switches the violation pulse based on the detection signal and detects the falling edge of the violation pulse, the switching circuit that switches the positive and negative detection edges, and 13 frames from the determined frame pulse falling edge.
A first mask generation circuit for generating a first mask signal having a bit width, and 15 bits from the determined frame pulse falling edge.
A second mask generation circuit that generates a second mask signal having a bit width is compared with the phase of the violation signal of the pole opposite to the frame pulse and the mask signal generated by the first mask generation circuit. 2-input AND gate and A
A frame pulse detection circuit including a toggle flip-flop that toggles according to the output of the ND gate and sends a switching signal.