KR930005834Y1 - Over current protective circuit - Google Patents

Abstract

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Description

Over Current Protection Circuit

1 is a conventional circuit diagram.

2 is a circuit diagram according to the present invention.

3A and 3B are timing charts of FIG. 2, a chart is a timing chart when the retry function is enabled, and b chart is a timing chart according to filtering of the noisy signal.

* Explanation of symbols for main parts of the drawings

101 ~ 104: Flip-flop 105. 106: Oagate

107.108: Noah gate 109: Andgate

The present invention relates to an overcurrent protection circuit in a large power device, and more particularly, to an overcurrent protection circuit having an overcurrent protection and a retry selection function suitable for a signal source having a lot of noise components.

In large power equipment, the effect of current is so great that proper shut-off is necessary. The current is sensitive to the equipment used and the ambient conditions, so there are many noise signals. Therefore, if proper filtering is required and there is a function to check and release when there is a current interruption by a noisy signal source, much smoothness can be achieved in reliability and device operation.

When there is a device that does not need the check function, it can be selected and used to diversify the function.

In the case of an inverter, the present invention is useful because there are many components of noise noise (current component and actual noise component that the device can withstand).

The inverter output current is detected and converted into a digital signal to control the over-current current of the inverter by the inventive circuit. In other words, the inverter stops the operation when the microprocessor (CPU) determines that the over current.

In the prior art configuration, as shown in FIG. 1, an overcurrent trip input (OCT-IN) signal terminal is connected to a terminal RB of the flip-flop 1, and a + is connected to the input terminal D. 5V power is connected, and over current trip output signal (OCT-IN) is output to output terminal (Q) and used as current cutoff signal.

The retry signal Retry is input as a clock signal of the flip-flop 102 and the inversion output Q is connected to the clock terminal CLK of the flip-flop 101 through the NAND gate 109. As a result, the inverted output Q of the flip-flop 102 is high when the power is turned on, and the reset key input signal (RST-IN) is high, thus outputting the NAND gate 109. Becomes low and the overcurrent trip output signal OCT-OUT of the output Q of the flip-flop 101 becomes high and is recognized as a normal state.

When the overcurrent trip input signal OCT-IN enters the low state, the output Q of the flip-flop 101 is low because the bit is held by the terminal RB of the flip-flop 101. It should be recognized as an over carrent trip condition.

At this time, the state of the overcurrent trip output signal OCT-OUT does not change before a clock is input. On the other hand, when the overcurrent trip output signal OCT-OUT is low, the flip-flop 101 receives the retry signal RETRY that checks the state of the overcurrent trip input signal OCT-IN again. The output Q of the inverted output Q is changed from low to high through the NAND gate 109 and applied to the clock terminal CLK of the flip-flop 101 through the NAND gate 109. At this time, if the overcurrent trip input signal OCT-IN is high, the output Q of the flip-flop 101 does not change. If the overcurrent trip input signal OCT-IN is high, the output Q is low to indicate an overcurrent situation.

However, in such a prior art configuration, the overcurrent trip input signal OCT-IN carries a lot of noise signals, which causes many errors in circuit operation. In addition, since the overcurrent trip input signal OCT-IN is bitten by the terminal RB of the flip-flop 101, there is a problem that the selection of the retry function is not easy because the selection range of the operation retry function is narrow at the time of signal input. there was.

Accordingly, the present invention is to solve the above problems, as shown in FIG. 2, + 5V is connected to the input D of the flip-flop 101, and the clock terminal CLK is connected to the NAND gate 109. Is connected to an output terminal of the output terminal, and an overcurrent trip input signal OCT-IN is applied to the terminal RB, and its output Q is connected to an input terminal D of the flip-flop 102, and the output of the flip-flop 102 is (Q) is connected to the input (D) of the flip-flop 103, and the output (Q) of the flip-flop 101 and 103 is an overcurrent trip output signal (OCT-OUT) through the oragate 105 And a retry (RETRY) and a write signal WR from the CPU such as a microprocessor to be applied to the clock terminal CLK of the flip-flop 104 through the NOA gate 107. The disretry signal DISRETRY and the write signal WR used when disregarding the signal are passed through the noar gate 108 and the reset signal RESET and no gay An oragate 106 for ORing the output signal of the 108 is connected and the terminal RB of the flip-flop 104 is connected through the oragate 106, and the inverted output Q of the flip-flop 104 is connected. Is a configuration in which the reset key is connected to the clock terminal CLK of the flip-flop 101 through the input signal RST-IN and the NAND gate 109.

Therefore, in the normal state, when the overcurrent trip input signal OCT-IN is high, the output Q of the flip-flops 101, 102, and 103 becomes high, so the overcurrent trip output signal OCT-OUT of the oragate 105 is It goes high to indicate normal state.

On the other hand, when the overcurrent trip input signal OCT-IN is low (abnormal state), the output Q of the flip-flop 101 becomes a loop and the output Q of the flip-flop 102 at the rising edge of the clock CLOCK. Further, at the next rising edge, the output Q of the flip-flop 103 becomes low, and the overcurrent trip output signal OCT-OUT of the OR gate 105 becomes low.

At this time, when the DISRETRY signal is low and the retry and the write signal WR are low, the output of the NOA gate 107 becomes high from low to the output of the NOA gate 108. Since it is high, the output of the oragate 106 depends on the reset signal RESET, and if the abnormality of the power supply does not occur, the reset signal RESET remains high, so the output of the oragate 106 becomes high. The state of flip-flop 104 is not changed. Therefore, the inverted output Q of the flip-flop 104 is changed from high to low by the output of the noah gate 107 changed from low to high so that the output of the NAND gate 109 goes from low to high, and the flip-flop ( The high signal of the data value (+ 5V) of the input D is displayed at the output terminal Q by being applied to the clock terminal CLK of 101. At this time, if the overcurrent trip input signal OUT-IN is high, the output Q of the flip-flop 101 becomes high, and the output Q of the flip-flop 102 becomes high at the rising edge of the clock CLOCK. At the next rising edge of the clock, the output Q of the flip-flop 103 becomes high, and the overcurrent trip output signal OCT-OUT of the oragate 105 becomes high.

In other words, the solid line in FIG. 3a shows each waveform when the overcurrent trip input signal OCT-IN continues to enter, and the dotted line shows the retry signal when the overcurrent trip input signal OCT-IN goes high before the ret. This indicates that the overcurrent trip output (OCT-OUT) signal returns to the normal state.

In addition, when the over current trip input signal OCT-IN is low and the distrit is high (no retry function is selected). Since the output of the NOA gate 108 is always low and the output of the ORGATE 106 is always low, the inverted output Q of the flip-flop 104 becomes high so that the reset key input (RST-IN) signal is low. If not, the output of the NAND gate 109 is not changed, so the retry signal RETRY is ignored and the reset key input signal RST-IN can change the state of the flip-flop 101.

As shown in FIG. 3B, the output ⑥ of the NAND gate 109 does not change even when the retry signal is input, so that the state of the flip-flop 101 does not change. Thus, as shown in FIG. 3B, the noise signal of the overcurrent trip input signal OCT-IN is filtered through the signals ①②③ of the output terminal Q of each of the flip-flops 101, 102, and 103, and the overcurrent trip output signal OCT-OUT. ) Will not appear. When the retry is low, the retry function is executed. When the retry is high, the retry function is ignored.

In addition, the operation of stopping according to the distry state and the retry state as described above is performed by the CPU in a process as shown in FIG.

Therefore, the overcurrent protection circuit according to the present invention removes short signals by adding two flip-flops to the input signal (OCT-IN), which is weak to noise, and thus has an effect of improving reliability, and also has a retry function. By widening the range of choices, the retry function can be performed, and the retry function is not diversified in devices that do not need the retry function.

Claims (1)

Connect the flip-flop 101 which applies a normal or current cut-off overcurrent trip output signal OCT-OUT in accordance with the overcurrent trip input signal OCT-IN, and input the retry and reset signals. The flip-flop 104 that applies the inverted output Q signal, the output signal of the flip-flop 104, and the reset key input signal (RST-IN) by the logical combination of the clock stage of the flip-flop 101 ( In the overcurrent protection circuit formed by connecting a NAND gate 109 for applying a pulse signal to CLK, the clock terminal CLK of the flip-flop 104 is formed by logically combining the retry signal RETRY and the write signal WR. NOR gate 107 for outputting the NOR gate 107, a NOR gate 108 for logically combining the write signal WR and the distritry signal DISRETRY inputted to the NOR gate 107, and the NOR gate 107 Input terminal RB0 of the flip-flop 104 by combining the output signal of the 108 and the reset signal RESET. The output terminal corresponding to the overcurrent trip input signal OCT-IN and the power supply 5V supplied from the output terminal Q of the flip-flop 101 and the input terminal D from the output terminal Q of the flip-flop 101 is input to the input terminal ( A flip-flop 102 that is applied by D) and outputs according to the pulse signal of the clock stage CLK, and the output Q of the flip-flop 102 is inputted and output according to the pulse signal of the clock stage CLK. The flip-flop 103, the output signal of the flip-flop 101 and the output signal of the flip-flop 103 are logically combined to provide a steady state signal and filtered current cut-off overcurrent trip output signal (OCT-OUT). An overcurrent protection circuit comprising an oragate 105 to be applied.