JPS6020254A - デ−タ処理装置 - Google Patents

デ−タ処理装置

Info

Publication number
JPS6020254A
JPS6020254A JP58127569A JP12756983A JPS6020254A JP S6020254 A JPS6020254 A JP S6020254A JP 58127569 A JP58127569 A JP 58127569A JP 12756983 A JP12756983 A JP 12756983A JP S6020254 A JPS6020254 A JP S6020254A
Authority
JP
Japan
Prior art keywords
cache memory
data
cache
address
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58127569A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0136133B2 (enExample
Inventor
Yoshiharu Ono
大野　義治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58127569A priority Critical patent/JPS6020254A/ja
Publication of JPS6020254A publication Critical patent/JPS6020254A/ja
Publication of JPH0136133B2 publication Critical patent/JPH0136133B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP58127569A 1983-07-15 1983-07-15 デ−タ処理装置 Granted JPS6020254A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58127569A JPS6020254A (ja) 1983-07-15 1983-07-15 デ−タ処理装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58127569A JPS6020254A (ja) 1983-07-15 1983-07-15 デ−タ処理装置

Publications (2)

Publication Number Publication Date
JPS6020254A true JPS6020254A (ja) 1985-02-01
JPH0136133B2 JPH0136133B2 (enExample) 1989-07-28

Family

ID=14963284

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58127569A Granted JPS6020254A (ja) 1983-07-15 1983-07-15 デ−タ処理装置

Country Status (1)

Country Link
JP (1) JPS6020254A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61193245A (ja) * 1985-02-21 1986-08-27 Hitachi Ltd 記憶制御方式
JPS61267149A (ja) * 1985-05-21 1986-11-26 Nec Corp デ−タ処理装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61193245A (ja) * 1985-02-21 1986-08-27 Hitachi Ltd 記憶制御方式
JPS61267149A (ja) * 1985-05-21 1986-11-26 Nec Corp デ−タ処理装置

Also Published As

Publication number Publication date
JPH0136133B2 (enExample) 1989-07-28

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