JPS60194338U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS60194338U
JPS60194338U JP1984081358U JP8135884U JPS60194338U JP S60194338 U JPS60194338 U JP S60194338U JP 1984081358 U JP1984081358 U JP 1984081358U JP 8135884 U JP8135884 U JP 8135884U JP S60194338 U JPS60194338 U JP S60194338U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
semiconductor
semiconductor device
circuit
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984081358U
Other languages
Japanese (ja)
Inventor
憲明 角
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP1984081358U priority Critical patent/JPS60194338U/en
Publication of JPS60194338U publication Critical patent/JPS60194338U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はワイヤボンディング方式の従来の半導体装置を
示す構造図、第２図はフリップチップ方式の従来の半導
体装置を示す構造図、第３図は本考案による一実施例の
半導体装置を示す構造図である。 １・・・・・・半導体チップ、１ａ・・・・・・第１半
導体チップ、１ｂ・・・・・・第２半導体チップ、２・
・・・・・パッケージ、３・・・・・・リード、４・・
・・・・ボンディングワイヤ、５・・・・・・蓋、６・
・・・・・セラミック基板、７・・・・・・配線パター
ン、８・・・・・・ピン、９・・・・・・金属粒。なお
、各図中同一符号は、同一または相当部分を示すものと
する。FIG. 1 is a structural diagram showing a conventional semiconductor device using a wire bonding method, FIG. 2 is a structural diagram showing a conventional semiconductor device using a flip chip method, and FIG. 3 is a structural diagram showing a semiconductor device according to an embodiment of the present invention. It is a diagram. 1... Semiconductor chip, 1a... First semiconductor chip, 1b... Second semiconductor chip, 2...
...Package, 3...Lead, 4...
...bonding wire, 5...lid, 6.
... Ceramic substrate, 7 ... Wiring pattern, 8 ... Pin, 9 ... Metal grain. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] （１）表面に回路が形成された半導体チップを、上記表
面が向き合うように互いに重ね合せ、各回路間を導電材
を介して接続し、一方の半導体チップを、信号又は給電
用端子を有するパッケージに装着したことを特徴とする
半導体装置。(1) Semiconductor chips with circuits formed on their surfaces are stacked on top of each other so that the surfaces face each other, each circuit is connected via a conductive material, and one semiconductor chip is packaged with signal or power supply terminals. A semiconductor device characterized in that it is attached to. （２）各半導体チップはそれぞれ機能の異なる回路を有
することを特徴とする実用新案登録請求の範囲第１項記
載の半導体装置。(2) The semiconductor device according to claim 1, wherein each semiconductor chip has a circuit with a different function.
JP1984081358U 1984-06-01 1984-06-01 semiconductor equipment Pending JPS60194338U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984081358U JPS60194338U (en) 1984-06-01 1984-06-01 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984081358U JPS60194338U (en) 1984-06-01 1984-06-01 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS60194338U true JPS60194338U (en) 1985-12-24

Family

ID=30628071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984081358U Pending JPS60194338U (en) 1984-06-01 1984-06-01 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS60194338U (en)

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