JPS59189250U - Mounting package for semiconductor elements - Google Patents
Mounting package for semiconductor elementsInfo
- Publication number
- JPS59189250U JPS59189250U JP8445583U JP8445583U JPS59189250U JP S59189250 U JPS59189250 U JP S59189250U JP 8445583 U JP8445583 U JP 8445583U JP 8445583 U JP8445583 U JP 8445583U JP S59189250 U JPS59189250 U JP S59189250U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor elements
- mounting package
- center
- semiconductor element
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図乃至第4図は背景技術を示す図で、第1図は平面
図、第2図は側面図、第3図は平面図、第4図は第3図
の裏面図、第5図及び第6図はこの考案の一実施例を示
す図で、第5図は平面図、第6図は裏面図である。Figures 1 to 4 are diagrams showing the background art, where Figure 1 is a plan view, Figure 2 is a side view, Figure 3 is a plan view, Figure 4 is a back view of Figure 3, and Figure 5. 6 are views showing an embodiment of this invention, FIG. 5 is a plan view, and FIG. 6 is a back view.
Claims (1)
半導体素子を実装し、半導体素子と回路線をワイヤーボ
ンディングし、回路線に基板裏面の電極に至るスルホー
ルを非直線状配列に配置してなる半導体素子の実装パッ
ケージ。A semiconductor element is mounted in the center of an electric circuit board that allows circuits to be formed radially from the center, the semiconductor element and circuit lines are wire-bonded, and through-holes are arranged in a non-linear arrangement in the circuit lines to reach the electrodes on the back of the board. Mounting package for semiconductor elements.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8445583U JPS59189250U (en) | 1983-05-31 | 1983-05-31 | Mounting package for semiconductor elements |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8445583U JPS59189250U (en) | 1983-05-31 | 1983-05-31 | Mounting package for semiconductor elements |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59189250U true JPS59189250U (en) | 1984-12-15 |
Family
ID=30214404
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8445583U Pending JPS59189250U (en) | 1983-05-31 | 1983-05-31 | Mounting package for semiconductor elements |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59189250U (en) |
-
1983
- 1983-05-31 JP JP8445583U patent/JPS59189250U/en active Pending
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