JPS5937732U - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5937732U JPS5937732U JP13396082U JP13396082U JPS5937732U JP S5937732 U JPS5937732 U JP S5937732U JP 13396082 U JP13396082 U JP 13396082U JP 13396082 U JP13396082 U JP 13396082U JP S5937732 U JPS5937732 U JP S5937732U
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- electrode surface
- insulator
- chip
- surface side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図、第2図はそれぞれ従来の半導体装置の電極引き
出し構造を示す平面図と斜視図、第3図以下は本考案に
よる半導体装置の実施例を示すもので、第3図は平面図
、第4図は部分断面分解図、第5図は引き出しパターン
を示す平面図、第6図は端子配列の他の実施例を示す平
面図である。
図において、5はチップ、8は電極、9はパッケージ、
10は絶縁体、11は接触子、12は端子、13は引き
出しパターンをそれぞれ示す。1 and 2 are a plan view and a perspective view, respectively, showing the electrode lead-out structure of a conventional semiconductor device, and FIG. FIG. 4 is a partially exploded cross-sectional view, FIG. 5 is a plan view showing a lead-out pattern, and FIG. 6 is a plan view showing another embodiment of the terminal arrangement. In the figure, 5 is a chip, 8 is an electrode, 9 is a package,
10 is an insulator, 11 is a contact, 12 is a terminal, and 13 is a lead-out pattern.
Claims (1)
意の位置に配置すると共に、 このチップの電極面側に装着して電極面をカバーする絶
縁体を備え、 この絶縁体の電極面側の面には、チップの各電極と対向
する位置に、対応する電極に接続される導体を備え、反
対側の面には、搭載基板の接続手段と対応する規則性で
端子を配列し、該端子と前記の電極面側の導体とは、絶
縁体において互いに接続されていることを特徴とする半
導体装置。[Claims for Utility Model Registration] The electrode of a chip equipped with a semiconductor integrated circuit is arranged at any position on the electrode surface, and an insulator is attached to the electrode surface side of the chip to cover the electrode surface. , The electrode surface side of this insulator is provided with a conductor connected to the corresponding electrode at a position facing each electrode of the chip, and the opposite surface is provided with a rule corresponding to the connection means of the mounting board. 1. A semiconductor device, characterized in that terminals are arranged in a matrix, and the terminals and the conductor on the electrode surface side are connected to each other through an insulator.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13396082U JPS5937732U (en) | 1982-09-03 | 1982-09-03 | semiconductor equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13396082U JPS5937732U (en) | 1982-09-03 | 1982-09-03 | semiconductor equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5937732U true JPS5937732U (en) | 1984-03-09 |
Family
ID=30301999
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13396082U Pending JPS5937732U (en) | 1982-09-03 | 1982-09-03 | semiconductor equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5937732U (en) |
-
1982
- 1982-09-03 JP JP13396082U patent/JPS5937732U/en active Pending
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