JPS6019167B2 - digital filter - Google Patents

Description

[Detailed description of the invention] This invention relates to digital filters.

Typical conventional digital filters discretely sample the input amount at appropriate time intervals, find the difference between these sampled values, and use this difference value to establish a differential equation that satisfies the desired characteristics. It was configured to do so. However, such digital filters require multipliers, dividers, and delay circuits, making their construction complex. Furthermore, there are errors caused by the multipliers and dividers, and errors caused by using the calculation results as input again. There were problems such as the difficulty of real-time processing due to accumulation and sampling. This invention was made in view of these points,
The present invention provides a digital filter with a simple configuration and excellent accuracy and response characteristics.

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. FIG. 1 shows the configuration of a digital filter according to the present invention. In FIG. 1, 10' is a subtracter, 2 up/down counters, and 30 is a numerically controlled frequency divider.

Subtractor 10 has input VII and up/down counter 2
A signal representing the difference in magnitude from the output Vc21 of 0 (hereinafter referred to as
output VR12) and a signal representing the polarity of the difference signal (hereinafter referred to as SI3). The numerically controlled frequency divider 30 divides the clock pulse frequency o31 and outputs a pulse frequency 32 having a frequency proportional to the magnitude of the output VR12 of the subtracter 10. up/down counter 20
uses the output 32 of the numerically controlled frequency divider 30 as a count input, and according to symbol S13, it counts up when the input VII is larger than the output Vc21, and counts down when the input 11 is smaller than the output Vc21. Numerical control frequency divider 30
This can be realized using, for example, a known DDA (Digital Differential Analyzer). One row is shown in FIG. In Figure 2, 33 is full adder 3
4 is a register, 35 is an AND gate, and 36 is a counter. Full adder 33 has input VR12 and register 34
and the output 37 of , resulting in an output 38.
If there is an overflow at this time, the overflow output 39
occurs. Since the register 34 reads the output 38 every clock pulse o31, the input VR12 is added to the register 34 every clock pulse o31. As a result, the overflow output 39 is ANDed with the clock pulse generator o31 and the frequency of the output 40 is the input VR1.
It will be proportional to the size of 2.

This AND output 40 is divided by the counter 36 and output 3
Set it to 2. Assuming that the full adder 33 is used, the number of bits of the register 34 is 0, and the number of bits of the counter 36 is Q, the output number is Tama-VR.

If a numerically controlled frequency divider as shown in FIG. 2 is used as the numerically controlled frequency divider 30 of FIG. Gakugo = Rare vR (the sign can be found in SI3) holds true.

Now, considering the analog filter circuit shown in FIG. 3, which includes a resistor R50 and a capacitor 60, the following holds true.

From the mth equation and the '2)th equation, the digital
It can be seen that the time constant value outside the figure has the same function as the RCI-order analog filter.

The output Vc21 is the integral output, the output VR12 is the differential output, and the output SI3 is the sign of the differential output VR12. In analog circuits, problems arise with accuracy, changes in characteristics over time, changes in characteristics due to environment, etc., whereas the present invention uses a digital system, so it is possible to realize a circuit with high precision and whose characteristics do not change. Furthermore, in order to realize a high-order filter, an analog system requires a buffer amplifier between stages, and it is difficult to freely set the characteristics, whereas the digital system according to the present invention requires a buffer amplifier between stages. In the case of filter evening,
To realize an n-th filter, it is sufficient to simply connect n stages directly, and its characteristics can be freely set by the number of bits q and b2 of each stage and the frequency of the clock pulse number o. As is clear from the above description, according to the present invention, it is possible to obtain an excellent digital filter with a simple configuration, high accuracy and responsiveness, and characteristics that can be freely set.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing details of the numerically controlled frequency divider 30 in FIG. 1, and FIG. 3 is an analog filter circuit. In the figure, 1 is a subtracter, 20 is an up/down counter, 30 is a numerically controlled frequency divider, 33 is a full adder, 34 is a register, 35 is an AND gate, and 36 is a counter. Note that the same reference numerals in the figures indicate the same or corresponding parts. Figure 2

Claims (1)

[Claims] 1. Means for outputting a difference signal between the magnitudes of the input signal and output signal of a digital filter and a signal representing the polarity of this difference signal, and means for dividing a clock pulse to generate a pulse with a frequency proportional to the magnitude of the difference signal. and counting means for counting frequency pulses proportional to the magnitude of the difference signal in response to a signal representing the polarity of the difference signal, and using the counted value as an output signal of the digital filter. A digital filter featuring: