JPS59101920A - Digital filter - Google Patents

Abstract

PURPOSE:To make peripheral parts unnecessary and also to reduce an input/ output pin by constituting a titled filter by use of a reference signal generating means, a magnitude discriminating means, a frequency dividing means, a gate means, an up-down counter and a detecting means. CONSTITUTION:A digital signal input signal D1 and a reference digital signal D2 are used as an input of a magnitude sicriminating means 6 and magnitude is discriminated. Signals S1, S2 showing a magnitude relation of the signal D1 and D2 becme inputs S5, S6 of an up-down counter 9 together with an output S4 of a frequency dividing means 7, and a digital signal D3 of a binary number is obtained from the counter 9. The means 7 divides an inputted clock pulse S3, and generates and outputs a clock pulse of frequency being proportional to an absolute value of a difference between the signal D2 and the input D1, and it becomes a clock input of the counter 9. Also, in order to prevent overflow and underflow of the counter 9, the maximum value and the minimum value are detected by detecting means 10, 11, and the gate outputs S5, S6 of the signals S1, S2 are inhibited by controlling a gate means 8 by outputs S7, S8. In this way, no perkpheral parts are required.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a digital filter that obtains an output by adding frequency characteristics to a binary digital signal input.

Conventional configurations and their problems Recently, the digitalization of home VTRs, especially the servo system, has been active, and IC (integrated circuit) for digital servo has already been developed.
It has been commercialized and introduced as a. The aim of this digitalization is to reduce the number of peripheral parts of the adjustment station 2, reduce power consumption, improve reliability, support multi-functionality, etc., and a fairly large scale digitalization is being planned. However, the phase compensation circuit (hereinafter referred to as filter) that determines the characteristics of the servo system
At present, the filter is still constructed of a resistor and a large electrolytic capacitor.As a conventional example of such a filter, an analog integrating circuit is shown in FIG. FIG. 2 is a waveform diagram for explaining the operation.

The components of the analog integration circuit are an operational amplifier 1, an input resistor 2. This is the feedback capacitor 3. Now, the input voltage E1.
When a potential difference occurs across E2, a current flows through input resistor 2, charging capacitor 3 and producing output voltage E. changes.

Output voltage E. When il>a, the potential decreases (~11
, 14~t5), and when El-E2, the potential stops (1,~t2.t5~), and when Jl;1<E2, the potential increases (t2~t3). The transmission relation G(s) of this circuit is (8
) ATl ・・・・・・・・・(1) However,
'r1=C1R1r C1tri return M core tear?
3 O capacitance, H, is the resistance value of the input resistor 2, which is 0, that is, it functions as an integral bag element.

In FIG. 3, a feedback resistor 4 is added to the components in FIG. 1, and the transfer function G(S) is, however, r1-C1H1,
T2-C2R2 is the resistance value of the R external feedback resistor 4. (2
) is transformed into, which has the integral element and proportional element of equation (1). Note that the magnitude of the current flowing through the input resistor 2 is the same as that of the input voltage E1. Since it is proportional to the potential difference of E2, charging and discharging of the charge of the feedback capacitor 3 is also proportional. However, the output voltage E shown in FIG. The slope of the potential is 1, El
, E2.

When integrating the integral circuit in Figure 1 and the proportional + integral circuit in Figure 3 explained above, three input/output pins of operational amplifier 1 and two to three external C) 1 components are required. However, there was a problem in that the number of external parts and pins could not be reduced.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional problems, and aims to provide a digital filter in which all the constituent elements are digitalized.

Structure of the Invention The present invention includes a reference signal generating means for generating a binary digital signal serving as a reference, a magnitude determination between the output of the reference signal generating means and a binary digital signal input, and an output according to the magnitude relationship. and a size determining means for generating a signal, which receives the digital signal input, the output of the reference signal generation means, and a clock pulse, divides the frequency of the clock pulse, and divides the frequency of the digital signal input and the output of the reference signal generation means. a frequency dividing means for creating a clock pulse with a frequency proportional to the difference in the fertilizer device; a gate means for gating and outputting the output of the size determining means (or the output of the frequency dividing means); and an output of the gate means. and an up/down counter which receives as inputs the output of the frequency dividing means (or the output of the magnitude determining means and the output of the gate means), detects the maximum value and minimum value of the up/down counter, and controls the gate means. The digital filter is provided with first and second detecting means for controlling the up-down counter and obtains a binary digital signal output from the up-down counter. A multiplication means for multiplying a signal by a coefficient, an addition means (or subtraction means) for adding (or subtracting) the output of the up-down counter and the output of the multiplication means, and the addition means (or subtraction means) By obtaining a binary digital signal output, it is possible to realize a digitized example + calculation circuit, and by completely digitizing it, external parts can be eliminated, and the circuit can be built into the IC. This also allows the number of human output pins to be reduced.

DESCRIPTION OF THE EMBODIMENTS FIG. 4 shows a first embodiment of the present invention, and FIG. 5 is an operational waveform diagram thereof.

In FIG. 4, 5 is a reference signal generation means for generating a binary digital signal as a reference, 6 is a magnitude discrimination means, and 7
8 is a frequency dividing means, 8 is a gate means, 9 is an up/down counter, 10 is a first detection means for detecting that the count value of the up/down counter 9 has exceeded a predetermined value, and 11 is the up/down counter 9. is a second detection means for detecting that the count value of Dl
is a binary digital signal input, D2 is a binary reference digital signal generated by the reference signal generating means 5, D3 is the output of the up/down counter 9, and S1 and S2 are the digital signals D1 and D2 of the magnitude determining means 6. , S3 is a clock pulse, S4 is the output of the frequency dividing means 7, S5. S6 is the output of the gate means 8;
S7. S8 is the output of the first and second detection means 10.11.

The digital signal human power D1 and the reference digital signal D2 are inputted to a size determining means 6, and the size is determined. The first and second digital signals L)1 and D20 of the magnitude determining means 6 represent a magnitude relationship. Second signal S1. S2 is connected to the amplifier down counter 9 together with the output S4 of the frequency dividing means 7 via the gate means 8.
Input S5. Set S6, and 2 from up/down counter 9.
The configuration is such that a base digital signal output D3 is obtained.

The frequency dividing means 7 divides the input clock pulse S3 to create and output a clock pulse with a frequency proportional to the absolute value of the difference between the reference digital signal D2 and the digital signal input D1, and outputs the clock pulse to the up/down counter 9. It is used as a clock input. Here, the reason why the frequency dividing means 7 creates a clock pulse with a frequency proportional to the absolute value of the difference between the reference digital signal D2 and the digital signal input D1 is to generate a clock pulse having a frequency proportional to the absolute value of the difference between the reference digital signal D2 and the digital signal input D1. This is to make it happen. This operation is exactly like the conventional manual resistance 2
In order to prevent overflow and underflow of the up/down counter 9, the first.
The maximum value is determined by the second detection means 10.11.

The minimum value is detected and the output S7. S8 controls the gate means 8 to control the first. Second signal S1. Gate output of S2 S5. The operation shown in FIG. 4 will be explained with reference to FIG. 6, which has a configuration that prohibits S6. When the magnitude determining means 6 determines the magnitude of the digital signal v1 and the reference digital signal D2, the value of bl is determined compared to D2. (0L) 1. The operation of the up/down counter 9 is switched up or down (or down or up) depending on whether the value is large or small. If the relationship of D2 is 1)>D (or Dl<D2), up-current (t2 to t3).

If D1=D2, stop counting (t1~t2.t3~14
．． 15~).

D (D (or Dl>D2) then down callan
2 (~11.14~16). Note that the operation of the output D3 of the up/down counter 9 shown in the figure is based on D2 and D when D1\D2.
Although the specific case is shown in which the absolute value of the difference between D2 and Dl is shown, in actual operation, the slope changes because the clock pulse is input from the frequency dividing means 7 in proportion to the absolute value of the difference between D2 and Dl. As a result, a digital filter having the function of an integral element can be realized by the first embodiment of the present invention shown in FIG. 4, which is completely digitalized. The time constant 1゛1 corresponding to equation (1) is, however, fck is the lowest frequency of the clock pulse S4 which is the output of the frequency dividing means 7 (the frequency when the absolute value of the difference between D2 and Dl is 1) ).

FIG. 6 shows a specific circuit example of the up/down counter 9 shown in FIG. 12 is a clock, <Rus input terminal, 13 is an up signal input terminal, 14 is a down signal input terminal, 15 to 1
8 is a digital signal output terminal. AND game) 19
．． The unit bit of the up/down counter is formed by the composite gate consisting of 20 and σR gate 21 and the flip-flop 22, and the up/down counter 9 can be constructed by connecting the required number of bits. This circuit operates as an up counter that uses the σ output of the previous flip-flop as a clock input when the input terminal 13 is II HII and 14 is °L'', and when the input terminal 13 is L'' and 14 is H11, the output of the previous flip-flop is It operates as a down counter that receives the Q output of . In addition, input terminals 13 and 14 are both 'L'
'', the clock is not input to each flip-flop and the counter stops. Digital signal outputs can be obtained from the output terminals 16 to 18. FIG. 7 shows a specific circuit example of the frequency dividing means 7 shown in FIG. 4. and the eighth
The figure is a waveform diagram for explaining the operation.

In FIG. 7, 23 is the input terminal of the clock pulse S3, and 24 to 27 are the LSB- of the absolute value ID1-D21 of the difference between the digital signal input D1 and the reference digital signal D2.
7MSH input terminal, 28 is the frequency-divided clock pulse S
4 output terminals, 29 to 32 are flip-flops forming a frequency dividing counter, 33 is an inverter for inverting the clock pulse, and 34 to 37 are absolute values ID1- of the difference between Dl and D2.
An AND gate inputs D21, the output of the inverter 33, and the outputs of the flip-flops 29 to 32 and performs a code, and 38 is an Of'L gate that takes the sum of the outputs of the AND gates 34 to 38.

The operation shown in FIG. 7 will be explained with reference to FIG. S3 is a clock pulse input to the frequency division counters 29 to 32, and Q1
~Q4 are each Q outputs.

1-i1 to G4 are the outputs of the AND gates 34 to 37 when the input terminals 24 to 27 are all H''.In this case, the reference digital signal D2 is 11000J and the digital signal input D
If 1 is "11o1J" or "0011",
The absolute value ID1-L)21 of the difference between Dl and D2 is “0101
Since it is J, AND gate 34.36 opens and 35.
37 is closed, and five clock pulses can be output as the output S4 of the oR gate 38 in one cycle of the frequency division counter. That is, the absolute value ID of the difference between Dl and D2, D
21 can be obtained as the divided output S4.

FIG. 9 shows a second embodiment of the present invention, in which multiplication means 39. Addition means 40 is added. That is, in the multiplication means 39, the digital signal input D1
The output D4 obtained by multiplying by the coefficient K is added to the output i)3 of the up/down counter 9 in the adding means 4o, and the obtained output D5 is used as a digital signal output. This makes it possible to realize a proportional-sufficient integral circuit in which a proportional element is added to the integral element of the first embodiment. “f2/T1 in equation (3) is T2/T1=K (6
) can be obtained as

FIG. 10 is a waveform diagram for explaining the operations of FIGS. 4 and 9. Now, the digital signal input v1 is at time t. is the minimum value at time t1, increases from time t1, becomes equal to the reference digital signal D2 at time t2, increases again from time t3, reaches the maximum value at time t4, decreases from time t6, and becomes equal to the reference digital signal D2 at time t7. It becomes equal to D2, decreases again from time t8, becomes the minimum value at time t1, increases from time t12, becomes equal to D2 at time t13, continues to increase, becomes constant at time t15, and becomes a constant value at time t.
16, becomes equal to D2 at time t1□, but still decreases, becomes a constant value at time t18, increases from time t19, becomes equal to D2 at time t1°, but still increases, and becomes a constant value at time t21. , decreases from time t22, becomes equal to D2 at time t23, still decreases, and becomes a constant value at time t24. Further, a case is shown in which the reference gage signal D2 is the center value of the digital signal human power L11.

The output D3 of the up/down counter 9 shows that the relationship between the digital signal D and the reference digital signal D2 is Dl>
This shows an example of an operation in which the counter counts up when D2 and counts down when Dl<D2, and stops counting when D1=D2. In addition, L)1. D2
．． D3 are each displayed in analog form.

Here, when the digital signal input D1 undergoes the above-mentioned state change, the output of each means changes as follows. The first signal S1 of the size determining means 6 is 13 to t7·113.
The period from t17 to t20 to t23 is II M II, and the other periods are °゛L'', and the second signal S2 is from to to t2
・The period from t8 to t13, 117 to t20, and t23 is H
'', the other period becomes L''. On the other hand, first detection means 10 detects the maximum value of the output D3 of the up/down counter 9.
The output S is L'' during the period t6 to t9 and H during the other periods.
'', and the output S of the second detection means 11 that detects the minimum value is
8, the period from t11 to t14/t25 is L'' and the other period is H''. However, the output S5 of the gate means 8 is 1-1 1 -1 . 1 -1 period is lH
l''35113, 17 20 23, the other period is I L l'', and the output S6 is to~t2
．． t8~t11r t17~t20+'23~t25
The period is H°' and the other periods are L''.

As described above, the up/down counter 9 is controlled by the gate means 8.
When the output ss of is I HII, II L II, count up 5 times 6 +1 L II, II HI+
It counts down when both are l L +'', and stops counting when both are l L +''.

Note that the output S7. Replace S8 and output S6゜S6
The operation of the up/down counter 9 can be reversed by exchanging the numbers, and this is simply a matter of polarity. however,
At this time, the addition means 41 must be a subtraction means, and must be configured to subtract D4 from D3.

In the second embodiment of the present invention described above, the multiplication means 3
If 9 is a multiplication by a power of 2, there is no need for a particularly complex multiplier circuit, and it can be handled by simply softening the bits of the digital signal input D1.

Also, 1st. In the second embodiment, the reference signal generating means 5
does not particularly require a gate circuit or the like, and can simply generate a fixed binary digital signal of IIHI+ or L''.

Further, the up-fist-down command to the up-down counter 8 is output by the output S1. A configuration using either one of S2 is possible, and the gate means 8 uses the output S1. It goes without saying that the objective can be achieved in the same manner by adopting a configuration in which the output S4 of the frequency dividing means 7 is gated instead of gating S2.

Effects of the Invention The digital filter of the present invention can realize an integrating circuit with a relatively simple configuration using a reference signal generation means, a magnitude discrimination means, a frequency dividing means, a gate means, an up/down counter, and first and second detection means. Furthermore, by using multiplication means and addition means (or subtraction means), it is possible to realize a proportional + integral circuit, which does not require any peripheral components, and can be used as an internal circuit of the iC, eliminating the need for the number of pins. The effect is significant.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an example of a conventional filter, Figure 2 is a block diagram showing an example of a conventional filter.
3 is a block diagram showing another example of a conventional filter. FIG. 4 is a block diagram showing a first embodiment of the digital filter of the present invention. FIG. 5 is a diagram showing its operating waveforms. , FIG. 6 is a specific circuit diagram of the up/down counter, FIG. 7 is a specific circuit diagram of the frequency dividing means, FIG. 8 is its operating waveform diagram, and FIG. 9 is a block diagram of the second embodiment of the digital filter of the present invention. 10 are detailed operational waveform diagrams of the first and second embodiments. 5... Reference signal generation means, 6... Size discrimination means, 7... Frequency division means, 8... Up/down counter, 10...・First detection means, 1
1... Second detection means, 39... Multiplication means, 40... Addition means (or subtraction means) 0 Name of agent Patent attorney Toshio Nakao and 1 other person 1st
Figure 2 Figure 3 Figure 3, Figure 6

Claims (1)

[Claims] (1) A reference signal generating means for generating a binary digital signal serving as a reference; and an output of the reference signal generating means;
a magnitude determining means for determining the magnitude of a base digital signal input and generating an output according to the magnitude relationship; the digital signal input, the output of the reference signal generating means, and a clock pulse are input, and the clock pulse is a frequency dividing means for dividing the frequency to create a clock pulse having a frequency proportional to the absolute value of the difference between the digital signal input and the output of the reference signal generating means; an output of the magnitude determining means; and an output of the frequency dividing means. an up/down counter which receives as input either the output of the gate means and the output of the frequency dividing means, or the output of the magnitude determining means and the output of the gate means; It is characterized by comprising first and second detection means for detecting the maximum value and minimum value of the up-down counter and controlling the gate means, and obtaining a binary digital signal output from the up-down counter. digital filter. (2) A reference signal generating means for generating a binary digital signal as a reference, and determining the magnitude of the output of the reference signal generating means and the binary digital signal input, and generating an output according to the magnitude relationship. A size determining means receives the digital signal input, the output of the reference signal generating means, and a clock pulse as input, divides the frequency of the clock pulse, and calculates the difference between the digital signal input and the output of the reference signal generating means. a frequency dividing means for creating a clock pulse with a frequency proportional to the absolute value; a gate means for gating and outputting one of the output of the magnitude determining means and the output of the frequency dividing means; an up-down counter which receives as input the output of the frequency determining means or the output of the size determining means and the output of the gate means, and a maximum value of the up-down counter; Second
a detection means, a multiplication means for multiplying the digital signal input by a coefficient, and an addition or subtraction means for adding or subtracting the output of the up/down counter and the output of the multiplication means, A digital filter characterized by obtaining a signal output.