JPH0382223A - A/d converter - Google Patents

Abstract

PURPOSE:To eliminate the need for a signal level conversion section by revising a prescribed integration time with respect to analog signal to be converted having a level over a wide range in response to a level of a nonconverting analog signal. CONSTITUTION:Even when an analog signal Ao is a signal whose level is changed over a wide range, an integration time T2y is present in response to the analog signal Ao to make the integration value E2 to an integration value at which the signal processing is implemented without hindrance at a signal processing section 15, resulting in converting the analog signal Ao into a digital signal Do easily. Thus, no signal level conversion section is required, the constitution is simplified and the manufacture is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an AD converter capable of converting an input analog signal into a digital signal over a wide range by 6X, in particular,
This invention relates to a converter that has a simple configuration and is easy to manufacture.

[Conventional technology]

-1 In the industrial process, the voltage signal of millivolts output by a thermocouple is converted into a voltage signal of the order of volts, such as a 1 to 5 [v] flaw signal, which is a unified signal specified by the NEC (International Electrotechnical Commission). leading to a voltage signal of Conventionally, an AD converter having the configuration shown in FIG. 5 has been used to convert an analog signal existing over a wide level range of 1000 times or more into a digital signal using a single AD converter.

In FIG. 5, l is the feedback resistance R□, R of the operational amplifier 2.
The voltage gain is changed by switching 0 with a changeover switch Sg. Resistor R0I R1□R1
0, a signal level conversion section consisting of a switch Sg and an operational amplifier 2, Ai is a negative polarity voltage signal input to the conversion section 1, and 3 is an analog voltage signal AO outputted from the conversion section 1 b''.
is inputted via the open/close switch S, and the reference voltage IEVs of negative polarity output from the reference voltage generating circuit 40s is inputted via the open/close switch St.1. and integrating capacitor C
Both ends of i are short-circuited or opened by opening/closing switch 01 So. It is an integrator circuit consisting of a resistor Ri, a capacitor C1, a switch S, and an operational amplifier 5. 6 is an H level when the output voltage E of the integrator circuit 3 is input and IEI≧jE, where JE is a positive minute DC WE. Next door+
A comparator that outputs a binary signal 6a that becomes L level when E+<jig, 7 is a clock pulse train signal 8a that outputs the binary signal 6a and a clock pulse generation circuit s bS
and O; is an input AND circuit. In this case, the signal level converter 1 is designed to be able to switch the voltage gain b in stages bZ, over three or more stages! t[IE
In some cases, the VC is configured so that the gain b1 can be switched.

In FIG. 5, the above-mentioned switches S, , S.

Gaminli! i5 unit 9b- Output signals 9aQ9bK, which are binary signals, are respectively driven by the signals 9aQ9bK. When the signal 9a19b/)' becomes L level, the circuit is opened.The 1 frequency divider 9 then performs a predetermined frequency division operation on the input clock pulse train signal 81, which will be described later. It is configured to output signals 9a and 19b periodically in a time-dependent manner, and furthermore, in FIG. The switch S is driven by the output signal 101 of the NOR circuit 10 and the output signal 113 of the AND circuit 11 inputted to the output signals 6a and b'' of the comparator 6.

The circuit is also configured to close the circuit when the input signal 11a goes to the H level, and to open the circuit when the input signal 11a goes to the L level. 12, when the pulse train signal 8a and the H-level comparator output signal 6a are input to the AND circuit 7, the pulse train signal 7a output from the AND circuit 7 and the output signal 10a of the NOR circuit 10 are input, and When the signal 10116SH is at the level, a counting operation is performed to count the pulses constituting the signal 7a, and when the signal 10a is at the L level, the pulse count value N is calculated by the above counting operation.
A counter 13 is inputted with a signal 12a representing the pulse count value N output from the counter 12 and a binary signal 6m, and when the shield number 6ab falls from the SH level to the L level, the counter 13 outputs the pulse count value represented by the signal 1211. Perform the @ calculation described later using the numerical value N.

Based on this calculation result, the signal converter 13 outputs the digital code signal Do representing the aforementioned analog voltage Al.
After calculating FE A o, If and aE A i are determined from the voltage AO with reference to the gain of the signal level converter l.

After that, it is configured to convert this Ai to DO[i. Reference numeral 14 denotes an AD converter yJ which is connected from each part shown in the figure gg5.

In the AD converter 14, when the power source 01 is turned on to the converter 14, the 1 frequency divider 9 sets the signal 9a to H level for a predetermined time 'ro, as shown in FIG. Immediately, the series of operations of setting the signal 9b to the H level for a predetermined time TI is continuously repeated at a predetermined period τ, so each part operates as described in "FK" below.

Figure 5 and #! In Fig. 6, the changeover switch 8g is used to set the '1tlE gain of the conversion unit 1 to the input voltage signal l so that the output voltage AO of the signal level conversion unit 1 becomes IEEE, which can be processed by the integration circuit 3. When the converter 14 is powered on after setting the gain according to the signal level to be input, and then the voltage signal At is input to the converter 1, the output terminal of the converter 1 receives the voltage A.
An electric power EEAO proportional to l appears. Then, in this case, the 1 frequency divider 9 outputs the H level signal 9 H1,s at time 1.s. In this case, the signals 9ae and 9b are both at L level, and the signal 10a is at H level. So time t
, when the frequency divider 9 sets the signal 9 to H level, the integrating circuit output voltage B becomes zero volts, so the binary signal 6a is reliably set to L level, and the NOR circuit output signal 10ab changes to XL level. Therefore, the count value N in the counter 412 is increased to zero by +1 sector. Then, from time t1 to time To
At time tttctg when tttctg has elapsed, the frequency divider 961 signal 90 is set to L level and the signal 9b is set to H level, so that the integrating circuit 3 outputs ti! The operation to integrate E A o is started, and the output type EE B 61 rises, so that when the state 61 of IBL Kono E occurs, the signal 6a6-H level is reached, so the pulse train signal 7a is output from the AND circuit 7. It turns out.

However, at time [, when time T has elapsed from 1 time t, the branch divider 9 sets the signal 9b to the L level, so the NOR circuit output signal 10a becomes the H level, and therefore the AND circuit output signal 11a goes to the H level. Since this integrated integration circuit 3 integrates the negative polarity reference voltage v8, 1! EEE gradually decreases. Also.

At time [, the signal 10a becomes H level, so the counter 1
The counting operation for the H.261 signal 7a is started, and the count value N in the counter increases. If the state of IEI<jB occurs at time 14, when time Tx has elapsed from time 1 [, then the signal 6a becomes L level, so at this time, the signal 11a becomes L level and the reference voltage ■8 is separated from the integrating circuit 3, the pulse train signal 7a is no longer output from the AND circuit 7, and a signal corresponding to the count value N at time t4 is output from the signal converter 13.

In the AD converter 14, each part 01 operates fjIh as described above, so if the input voltage Ai is a voltage that does not change over time, if the value of the voltage E at time t, K is El, then K
Equation (1) (6) is established with (1) being a proportionality constant, and Equation (2) is derived from this (1) equation. Then, the time Tx in equation (2) becomes a proportionality constant, and the pulse count value N at time [4]
Since it is clear that it is expressed as the product of Knowing that the voltage AO can be found from equation (3), b'-8
A. It's easy.

E ＝＝に＊ A Om 'l' ツに @ V8 @
TX , −, −・(1)i Ao =Vs −(Tx/T1) ・−
-----(2) A o = k IIVs * N/T
, = (33 In the AD converter 14, the signal converter 1
36"-Signal 6 a h's By falling from H level to L level, calculate AO on the right side of equation (3), and output signal D according to voltage 4i proportional to this AO. Then, at time t, 1, when a predetermined period τ has elapsed from time t, the branching device 9 again sets the signal 9a to the H level and then the signal 9b to the H level. In this case, even if the magnitude of
is set. As a result, in the case of the AD converter 14, the digital signal 1)o corresponding to the analog signal 1EAiK is output from the converter 13 at a period of τ. Then, the AD converter 14 performs the AD conversion operation as described above, so when the magnitude of the KWl pressure Ai changes during the above-mentioned time T, this converter 14 changes the magnitude input 06 to El. /
DC type EE equal to (K-Ts)
A digital signal DO corresponding to e is output.

[Problem to be solved by the invention]

Since the AD converter 14 is configured as described above, by appropriately selecting the voltage gain of the converting unit 1, the input voltage EEAi of the converting unit 1 is divided between the integrating circuit 3, the reference voltage generating circuit 4, and the combiner 46. A signal A at a voltage level that can be processed by the signal processing unit 15 consisting of switches S, , S,
OK to convert and therefore this converter 1
4 has the advantage that AD conversion can be performed for various input signals At having a wide range of signal levels by simply changing the voltage gain in the conversion section IK without changing the configuration after the signal processing section 15. case.

For each section after the signal processing section 15 where the permissible change range of the level of the voltage signal AO is limited, the analog wlFE signal Ai with a wide range of levels is converted into a digital signal])o
In order to convert to
- AD converter 14 because it is necessary! /c has a problem in that it has a complicated configuration. Furthermore, in this case, in order to improve the signal conversion accuracy of the converter 1, it is necessary to improve the accuracy of the characteristics of each electronic part in the converter 1.

From this point of view, the converter 14 also has the problem of being cumbersome to manufacture.

An object of the present invention is to provide an AD converter that can convert an analog voltage signal 71i with a wide range of levels into a digital signal DO without using the signal level converter 1, and that is simple in configuration and easy to manufacture. It's about getting.

[Means to solve the problem]

In order to achieve the above object, 1 according to the present invention, when performing an operation to zero the integral value obtained by integrating the analog signal to be converted for a predetermined period of time by integrating the reference analog signal, the reference analog signal is In an AD converter that measures an integration time and converts the analog signal to be converted into a digital signal based on the integration time, the AD converter is configured such that the predetermined time is variable.

[Effect]

With the above configuration, even if the analog signal to be converted b'' is a signal having a wide range of levels,
Predetermined integration time T! for this analog signal to be converted! By changing the level of the analog signal to be converted depending on the level of the analog signal to be converted, the integral value E obtained by integrating the analog signal to be converted for a time T, can be adjusted to the level of the voltage E1 shown in FIG. 6, that is, the signal mentioned above. It is clear that the signal level converter 1 described above is not required in this case because the voltage can be extremely easily reduced to a level that allows the signal processing 6 to be performed without any trouble in the processing section 15, so the configuration is simple and Easy-to-manufacture AD
Fcfg that the converter is obtained.

〔Example〕

FIG. 1 shows the first aspect of the present invention! t of one figure in the configuration diagram of 4 examples
gs diagram and J! ! The main points are that the signal level converter 1 is not provided, and a divider 16 is provided in place of the divider 9 in FIG. Same 411! In addition to outputting the binary signal 9a to lI,
5 to output four binary signals 16bl to 16b4, all of which correspond to the binary signal 9b described above, and an on/off switch 8.6 that is input via a 6L changeover switch S. The fifth
The signal converter 17 corresponding to the signal converter 13 in the figure changes from the input signal 6ab'hH level to the L level F6''-
By this, the output signal 12a of the counter 12 and the changeover switch S.

Switching switch linked to y-! -84, the digital code signal DO is output by performing the calculations described below using any one of the four pieces of time data held in the time data holding unit 18 inputted through the 84. It is configured.

Then, in this case, the signal 16 outputted from the 1 branching unit 16b1
b1 to 16b4 are the signals 9 output from the branch unit 16b1 as well.
When a falls from H level to L level by 6X, both become L.
The signal 16b1 rises from the H level to the H level by 6X, and after this, the signal 16b1 remains at the H level for a time T.

The signal 16b2 continues to be at the H level for a time □, the signal 16b3 continues to be at an H level for a time T■,
The signal 16b4 remains at the H level for a time T14. Here, 1 hour T□ to 'I't4 are different times. In addition.

1lc1, the 1st branch 16 differs from the 1st branch 9 in that the output signal 6i of the comparator 6 changes from the H level to the L level.
When the signal falls to the high level, after a predetermined time period T has elapsed, the above-described series of operations for setting the signals 9a#16bl to 16b4 to the H level are performed again. Further, the time T is stored in the time data holding section 18 mentioned above. - Four pieces of time data representing each of T*4 are held,
When the selector switch 8s selects one of the signals tsby from the signals 16bl to 16b4, the time data representing the H level duration Tzy of the selected signal 16by61M is transferred to the switch 8 linked to the switch S.
4, the data is selected from among the time data held in the holding unit 18 and input to the signal converting unit 17. Reference numeral 19 denotes an AD converter consisting of the various parts shown in the figure.

Since the AD converter 19 is configured as described above, when the :I source is turned on to this converter 19 by selecting the signal 16by with the switch S1, the analog signal input to the on/off switch S1 becomes the AO signal. If it is a current voltage having a voltage value, W! As shown in Fig. 2, the value of E increases linearly for the time T2Y after the output 91 of the integrating circuit 3 EE B 6' - time t and reaches the time t when time Tzy has elapsed since the time. become.

Time 1. After that, the integrating circuit 3 integrates the reference voltage flEV'sik, so that the voltage EE E 6" - linearly decreases to time t4.
When IEI becomes smaller than IB, the signal 6Il goes to L level rj, and at time t, one time T has elapsed from time t4.
, the signal becomes the 9a6SH level again, and as a result, following equation (1), equation (4) 6S holds true, so (4)
Equation (5) is derived from the equation.

B1 TomiKsAo*TzymK@Vs*Tx ・-,,
-(4) Aowk * Vs * N/T2Y
”” (5) Here, N is the counter 1 at time t.
When the signal 6a falls from the H level to the L level at time t4 in the input converter 19, the count value at 2 is counted.

Signal converter 1761. Count value N representing signal 12 a bz
The right side of equation (5) is calculated using
It is configured to output a digital signal representing the resulting AO])0.

In the AD converter 19, the signal 91 is set to the H level after a time T after the signal 6a becomes the L level, so it takes 1 hour T.
Regardless of the length of oy, the clock will never be later than 6% time t.

Since the AD converter 19 operates as described above.

In this case, even if the analog signal AO is a signal whose level changes over a wide range, the above-mentioned integration time T2y
By setting in advance according to the level of the analog signal AO, the integral value E shown in FIG. 2 can be made to the same extent as the integral value E shown in FIG. 6.

In other words, the signal processing unit 15 can obtain an integral value that can be processed without any problem, and as a result, the analog signal AO can be easily converted into the digital signal Do. In this case, it is clear that the signal level converter 1 shown in FIG. 5 is unnecessary. Therefore, the AD converter 19 can convert the analog signal AO whose level changes over a wide range into the digital signal Do. .This is a converter that is simple in W configuration and easy to manufacture.

FIG. 3 is a block diagram of a second embodiment of the present invention, and the difference from FIG.
0 Instead of the above-mentioned signals 16b1 to 16b4, one signal 20b, which becomes H level only during the integration time Tzz represented by the integration time indicator signal 22a, which is input to the branching device 20, is output in addition to the binary signal 9a. Furthermore, this frequency divider 20 is configured to output the signal 9m and the signal 20b in the same manner over time as in the case of the divider 16Q when the finger◆ signal 22a is input. and a signal converter 21b' corresponding to the signal converter 17 in FIG.

Counter output signal 12a and the above finger◆signal 22a 6S
and the signal 22a 6X
Using the integral time T2z represented by the input signal 22a and the count value N represented by the signal 12a6S, the right side of equation (6) corresponding to equation (5) is calculated to output the digital signal DO. and is provided with an integral time distribution ◆ signal generating section 22 which receives the signals 6a, 128, and 61 and outputs the finger ◆ signal 22a.

AOwk m Vs @N/T2z -----(
5) In this case, as shown in FIG. 4, when the input signal 616X falls from the H level to the L level, the signal generator 22 generates the count value N6'-(7) represented by the signal 12a.
Judge whether the formula is satisfied, and if it is satisfied, the first
If the signal 221a is not satisfied, the second signal 221 is output.
The count value determination unit 221 that outputs the integral time T2z and the predetermined initial value Tio of the integration time T2z are stored in advance, and when the calculation unit output signal 223116' is input, it outputs the already stored integral time storage value Tia as a signal. An integral time storage unit 222 updates the integral time value Tibrc represented by 223a and outputs a signal 222a representing the stored integral time, and when the second signal 221b is input, the signal 12 a bs A calculation unit that performs the calculation on the left side of equation (8) using the integral time Tia expressed and N8 shown in the above-mentioned equation (7), and outputs the above-mentioned calculation unit output signal 223a representing the integration time Tib of the calculation result. 223 and the first signal 221a
When is input, the storage unit output signal 222a is output as the above-mentioned stirring time indicator ◆ signal 22a, and when the first signal 221a is not input, the calculation unit output signal 223a is output as the indicator ◆ signal 221.
It is composed of a switching switch 224 that outputs as follows.

Reference numeral 23 in FIG. 3 is an AD converter consisting of various parts shown in the figure, and when this converter 231CV is turned on, it first converts the count value determination unit 2216 in FIG. 4 into a signal 221a.
is configured to output.

N5-jN≦N,! N5-1jN ・・・・・・
(7) (Ns/N)-Tia=Tib,-
, , (B) In equations (7) and (8), Ns is a reference count value set in advance, and jN is a margin value set for the count value N.

Since the AD converter 23 is configured as described above, it is clear that the integration time T2z represented by the integration time indicator ◆ signal 22a is equal to any one of the above-mentioned integration times Tio, Tia, and Tib. So in this case.

Integration time indicator ◆ The reference count value Nl in the signal generating section 22 is determined by the time T required for the counter 12 to obtain this count value N8.
The voltage Vs of opposite polarity to the open reference voltage Vs of S is applied to the integrating circuit 3.
If E4 is set to a count value such that the voltage EEK obtained by integration is equal to the voltage E1 or E, the analog signal AO is generated by the operation of the signal generator 22 as described above. is integrated for time Tgz in the integrating circuit 3, and the integral value E1 obtained is always a voltage near the voltage E4, so in the AD converter 23, as in the case of the AD converter 19, t EEL is Base S Den 8Evs
The signal converter 21 outputs a highly accurate digital signal Do corresponding to the analog signal AO based on the time Tx required to reach zero port by integrating .

Since the AD converter 23 performs AD conversion as described above, the converter 23 includes the converter 19 shown in FIG.
Compared to the above, there is an advantage b1 that the troublesome work of setting the integration time when the analog signal AO is integrated by the integrating circuit 3 in accordance with the level of the signal AO is unnecessary.

In FIG. 1, the switches S, , S select one signal or data from among four signals or data.The present invention is not limited to the above-mentioned number of four signals or data. This is obvious and needs no explanation.

〔Effect of the invention〕

As described above, in one aspect of the present invention, the integration time of the reference analog signal necessary for zeroing the integral value obtained by integrating the analog signal to be converted for a predetermined period of time by integrating the reference analog signal. In an AD converter that measures the integration time and converts the analog signal to be converted into a digital signal based on the integration time, the predetermined time is made variable.

Therefore, with the above-mentioned VC configuration, even if the analog signal to be converted is a signal with a wide range of levels, the predetermined integration time T for the analog signal to be converted is adjusted according to the level of the analog signal to be converted. By changing the integral value E! obtained by integrating the analog signal to be converted for a time T, The voltage can be extremely easily reduced to the level of voltage 1EE1 shown in FIG.

In this case, it is clear that the signal level converter 1 described above is not required, so the present invention has the advantage of providing an AD converter that is simple in structure and easy to manufacture.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention. FIG. 2 is an explanatory diagram of the operation of the main parts in FIG. 1. FIG. 83 is a configuration diagram of a second embodiment of the present invention. FIG. 4 is a view #lI of the main part in FIG. 3. FIG. 5 is a configuration diagram of a conventional ADfIIJ device. FIG. 6 is an explanatory diagram of the operation of the main parts in FIG. 5. 14, 19.23...AD converter, A11AO
...Analog voltage signal, E, B,, E,...
...Integrator circuit output voltage. vS...Reference analog electric EE, TX...
・Integration time, D. Notebook 2 Zujitsuji 6 Diagram

Claims (1)

[Claims] 1) Measure the integration time of the reference analog signal, which is necessary when performing an operation to zero the integral value obtained by integrating the analog signal to be converted over a predetermined period of time, by integrating the reference analog signal, and calculate this integration. An AD converter that converts the analog signal to be converted into a digital signal based on time, characterized in that the predetermined time is variable.