CN105391452A - Semiconductor device, analog-to-digital conversion method, onboard system, and measurement method - Google Patents

Abstract

The invention provides a semiconductor device, an analog-to-digital conversion method, an onboard system, and a measurement method. There is provided the semiconductor device including: an integrator that repeats integrating a first reference voltage after integrating an analog signal; a comparator that compares an output of the integrator and a second reference voltage; a counter circuit that counts a first integration time determined to integrate the analog signal, and a second integration time until the output of the integrator reaches the second reference voltage from start of integration of the first reference voltage; a calculation circuit that calculates a digital value of the analog signal based on the first and the second integration times; a control circuit that performs control so that the analog signal is input to the integrator while the counter circuit counts the first integration time; and an integration time update circuit that updates the first integration time counted by the counter circuit based on the second integration time counted thereby.

Description

Semiconductor device, analog-digital conversion method of solid, onboard system and method for measurement

the cross reference of related application

The application based on and the priority of No. 2014-169535th, the Japanese patent application requiring on August 22nd, 2014 to submit to, the open entirety by reference of this application is herein incorporated.

Technical field

The present invention relates to semiconductor device, analog-digital conversion method of solid, onboard system and method for measurement, and such as relate to analog signal integrator to obtain the technology of digital value.

Background technology

Have biproduct somatotype A/D as analog-digital conversion analog signal being converted to digital value to change.Usually, although biproduct somatotype A/D converter has degree of precision and more can support antimierophonic A/D converter compared with the transducer of other types, but it has the feature of the measurement of the signal being applicable to relatively slowly change, because it needs the time to change for A/D.Therefore, such as, in the onboard system of Engine Control System etc. such as needing high precision and noise resistivity, biproduct somatotype A/D conversion is performed.In such onboard system, because vehicle controls, so the precision that the Accuracy of measured value controls based on the measured value of the suction and discharge temperature etc. of such as engine.For this reason, high-precision A/D is needed to change in onboard system.

Such as disclose No. 1993-83135 and Japanese Unexamined Patent Application in Japanese Unexamined Patent Application to disclose in No. 1991-23719 and disclose biproduct somatotype A/D converter.

Summary of the invention

The object of the invention is the precision improving analog-digital conversion.

Other problems and new feature are by apparent in the description from this specification and accompanying drawing.

According to an embodiment, the first integral time of analog signal integrator and second integral time of reaching the second reference voltage to the output of integrator from the integration of the first reference voltage are counted determining by semiconductor device, and upgrade the first integral time based on the counted second integral time.

According to an above-mentioned embodiment, the precision of analog-digital conversion can be improved.

Accompanying drawing explanation

Above and other aspect, advantage and feature by more apparent from the description below some embodiment of carrying out by reference to the accompanying drawings, wherein:

Fig. 1 is the circuit diagram of the configuration of the semiconductor device illustrated according to embodiment 1;

Fig. 2 is the time diagram of the operation of the semiconductor device illustrated according to embodiment 1;

Fig. 3 is the figure of the difference illustrated according to the time of integration at each electromotive force for analog signal in the semiconductor device of embodiment 1;

Fig. 4 A is the figure of the transformed error that A/D converter is shown, and shows the transformed error of the semiconductor device according to comparative example;

Fig. 4 B is the figure of the transformed error that A/D converter is shown, and shows the transformed error of the semiconductor device according to embodiment 1;

Fig. 5 is the schematic diagram of the configuration that the vehicle wherein having installed the onboard system according to embodiment 2 is shown;

Fig. 6 is the block diagram of the summary of the configuration of the onboard system illustrated according to embodiment 2;

Fig. 7 is the block diagram of the detailed configuration of the onboard system illustrated according to embodiment 2;

Fig. 8 is the circuit diagram of the configuration of the semiconductor device illustrated according to embodiment 3;

Fig. 9 is the time diagram of operation when the N time conversion according to the semiconductor device of embodiment 3 is shown;

Figure 10 is the figure of the difference of the time of integration illustrated according to each electromotive force for analog signal in the semiconductor device of embodiment 3;

Figure 11 is the block diagram of the detailed configuration of the onboard system illustrated according to embodiment 4;

Figure 12 illustrates the time diagram changed by the A/D performed according to the transducer I/F unit of embodiment 4;

Figure 13 is the circuit diagram of the configuration of the semiconductor device illustrated according to comparative example;

Figure 14 is the figure that the passage of time exported according to the integration of the integrator in the semiconductor device of comparative example is shown; And

Figure 15 is the figure of the relation illustrated between the amplitude of analog signal and the time needed for conversion.

Embodiment

< precheck >

Before explanation embodiment, the scope of examination of being carried out in advance by the present inventor will be described.

The explanation > of the configuration of < comparative example

Figure 13 is the circuit diagram of the configuration of the semiconductor device 9 illustrated according to comparative example.Semiconductor device 9 is following biproduct somatotype A/D converters, and it has: switch 10 and 11; Integrator 12; Comparator 13; Counter circuit 14; Counting circuit 15; With control circuit 16.

The input of switch 10 and 11 pairs of integrators 12 switches.Particularly, switch 10 switches whether analog signal Van being inputed to integrator 12, and whether switch 11 to switches inputing to integrator 12 as the integration reference voltage V ref (the first reference voltage) of predetermined voltage.Switch 10 and 11 is operated according to the control undertaken by control circuit 16.

Integrator 12 is configured to comprise: resistor R; Capacitor C; With operational amplifier 120.Integrator 12 is the circuit by being carried out the input integral switched by switch 10 and 11.Integration is exported Vo and exports comparator 13 to by integrator 12.Integrator 12 passes through the control of the control circuit 16 mentioned later to repeat integration reference voltage V ref integration after by analog signal integrator according to switch 10 and 11.

The integration of integrator 12 is exported Vo with comparator 13 and benchmark voltage (the second reference voltage) compares, and detects whether integration output Vo is benchmark voltage (0V).When the integration output Vo of integrator 12 is benchmark voltage, comparator 13 exports detection signal to counter circuit 14.

Counter circuit 14 counts by the time T1 (first integral time) determining making integrator 12 by analog signal integrator, and exports signal to control circuit 16.In addition, counter circuit 14 to from integration reference voltage V ref by detecting that the integration of integrator 12 exports the time T2 (second integral time) that Vo reaches benchmark voltage and counts to comparator 13 the integration of integrator 12, and signal is exported to control circuit 16 and counting circuit 15.Hereinafter, the above-mentioned first integral time is referred to as time T1, and the above-mentioned second integral time is referred to as time T2.

Control circuit 16 based on counter circuit 14 output and switch 10 and 11 is controlled.Particularly, first controller 16 carries out control to switch 10 and makes analog signal Van side become ON (closing), and subsequently, switch 10 is remained ON until time T1 recorded by counter circuit 14.As mentioned above, when the time, T1 counted counter circuit 14 pairs, control circuit 16 pairs of switches 10 and 11 carry out control and make analog signal Van be input to integrator 12.When being counted out time T1 by counter circuit 14, control circuit 16 pairs of switches 10 carry out control and make analog signal Van side become OFF (disconnection), and carry out control to switch 11 and make integration reference voltage V ref side become ON.In addition, when time T2 recorded by counter circuit 14, switch 11 is controlled to disconnection by control circuit 16.

Counting circuit 15 is the circuit carrying out the digital value of calculating simulation signal based on the time T1 recorded by counter circuit 14 and time T2.The content of the calculating undertaken by counting circuit 15 will be mentioned later.

First the analog signal Van sampled during time T1 is carried out integration to time T1 according to above-mentioned configuration by semiconductor device 9, and next predetermined integral reference voltage V ref is carried out integration to time T2.In mode as above, analog signal Van is quantized by twice integration by semiconductor device 9, and as the electromotive force of A/D transformation result outputting analog signal Van.

The explanation > of the operation of < comparative example

Here, the operation of semiconductor device 9 will be described.Figure 14 illustrates that the integration according to the integrator 12 in the semiconductor device 9 of comparative example exports the figure of the passage of time of Vo.When analog signal Van is input to integrator 12, the integration of integrator 12 exports Vo to be increased together with t with the time of integration as Suo Shi formula (1) below.Note that reference character CR represents time constant.

Vo＝(Van/CR)t…(1)

Therefore, the formula (2) below the integration output Vo when having disappeared time T1 passes through is expressed.

Vo＝(Van/CR)T1…(2)

When disappeared time T1 time, control circuit 16 cut-off switch 10, and turn on-switch 11.As its result, integration reference voltage V ref is input to integrator 12.When integration to integration reference voltage V ref by integrator 12, integration export Vo and the time of integration t reduce pro rata.Now, the slope of change that integration exports Vo is determined by integration reference voltage V ref and time constant CR, and the amplitude no matter inputting analog signal Van how.Particularly, integration exports the slope of the change of Vo is Vref/CR.In addition, when the integration output Vo of integrator 12 becomes benchmark voltage (0V), comparator 13 exports detection signal to counter circuit 14.

The detection signal of counter circuit 14 device 13 based on the comparison, exports Vo to integration after the switch of integration reference voltage V ref side is become ON and reaches the time T2 that benchmark voltage (0V) counts and export counting circuit 15 to.

Here, the integration when having disappeared time T2 exports Vo and meets the relation illustrated by formula (3) below.

Vo＝(Van/CR)×T1+(Vref/CR)×T2＝0…(3)

Therefore, counting circuit 15 exports the A/D transformation result of the analog signal Van that the calculating that illustrated by formula (4) is below calculated.

Van＝﹣Vref×(T2/T1)…(4)

In addition, when formula (4) is deformed, obtain formula (5) below

T2＝(Van/(﹣Vref))×T1…(5)

Here, because integration reference voltage V ref and time T1 is constant, so result is time T2 depend on Van.That is, although how time T1 is constant to the electromotive force of no matter analog signal Van, time T2 depends on the electromotive force of analog signal Van and different.Particularly, as shown in figure 15, the electromotive force of analog signal Van is higher, and the time (T1+T2) needed for conversion becomes longer, and the electromotive force of analog signal Van is lower, and the time (T1+T2) needed for conversion becomes shorter.Note that in fig .15, transverse axis represent the time of integration t and the longitudinal axis represent integration export Vo.In addition, dotted line represents that the integration when the analog signal Van of maximum electrical potential is input to integrator 12 exports, solid line represents that integration when the analog signal Van of minimum potential is input to integrator 12 exports, and the integration when analog signal Van of electromotive force that chain-dotted line represents between maximum electrical potential and minimum potential is input to integrator 12 exports.

Because time T1 and T2 is sampled by counter circuit 14, so the resolution of time T1 and T2 depends on the frequency of the clock of operation counter circuit 14.For this reason, the resolution of time T1 and T2 is represented as the quantity of clock.Therefore, because the resolution of time T1 and T2 can increase, so likely carry out calculating simulation signal Van from the result of calculation of above-mentioned formula (4) with high accuracy the quantity of the clock that time T1 and T2 samples by being increased in semiconductor device 9.

The < scope of examination illustrates >

The present inventor checked ensuing two kinds of methods of the method as the quantity for increasing the clock of sampling to time T1 and T2.First method is for the method by increasing the resolution frequency of the clock that time T1 and T2 samples being increased to time T1 and T2.But, in this case, there is the problem that power consumption increases explicitly with increase clock frequency.Second method is the method for being increased the quantity to the clock that time T1 and T2 samples by time expand T1 and T2.But, when the method, such as with regard to being standardized as with regard to the A/D converter of product specification etc. at the integration terminating to be used for a conversion in predetermined period, owing to can not ensure to terminate conversion in predetermined period, can not by the problem extended simply so there is time T1 and T2.

Hereinafter, with reference to the accompanying drawings embodiment is described.The technical scope of embodiment note that because accompanying drawing is simplified, so narrowly can not be explained based on the description of these accompanying drawings.In addition, identical Reference numeral is attached to identical element, and will omit repeated description.

< embodiment 1>

Fig. 1 is the circuit diagram of the configuration of the semiconductor device 1 illustrated according to embodiment 1.Semiconductor device 1 is following biproduct somatotype A/D converter, and it has: switch 10 and 11; Integrator 12; Comparator 13; Counter circuit 14; Counting circuit 15; Control circuit 16; The time of integration refresh circuit 17; With memory circuit 18.

As mentioned above, semiconductor device 1 be according to the difference of the semiconductor device 9 of comparative example: except being respectively configured to of the semiconductor device 9 according to comparative example, by the time of integration refresh circuit 17 and memory circuit 18 be added into former device.Although in an embodiment, describe the configuration of the memory circuit 18 providing the output storing counting circuit 15, semiconductor device 1 does not need necessarily to store result of calculation.Therefore, when semiconductor device 1 does not store result of calculation, do not need to provide memory circuit 18.

According in the semiconductor device 1 of embodiment 1, the input of control circuit 16 pairs of integrators 12 controls to make integrator 12 perform the integration of analog signal Van and integration reference voltage V ref once within the intended conversion cycle, and the time of integration, refresh circuit 17 upgraded the time T1 in next change-over period based on the time T2 in the current change-over period.Hereinafter, the detailed configuration of semiconductor device 1 will be described.

The time of integration, refresh circuit 17 was the circuit upgrading the time T1 counted by counter circuit 14 based on the time T2 counted by counter circuit 14.Note that in refresh circuit 17 time of integration update time T1 ad hoc approach will mention later.The time T2 counted by counter circuit 14 is input to refresh circuit 17 time of integration.In addition, the time of integration refresh circuit 17 output, the time T1 be namely updated, is input to counter circuit 14 and counting circuit 15.

When time T1 is updated by refresh circuit 17 time of integration, counter circuit 14 counts with the time T1 be updated the time of integration to analog signal Van.When time T1 is updated by refresh circuit 17 time of integration, counting circuit 15 utilizes the time T1 be updated to perform the calculating illustrated by above-mentioned formula (4).

Memory circuit 18 is the circuit storing the A/D transformation result obtained by the calculating of counting circuit 15 as mentioned above.Memory circuit 18 is such as register.

In addition, control circuit 16 exports on/off signal SWVan to switch 10, and exports on/off signal SWVref to switch 11.Counter circuit 14 exports switching over signal S1 to control circuit 16.Comparator 13 exports comparator output signal S2 to counter circuit 14.Counter circuit 14 time T2 is exported to counting circuit 15 and the time of integration refresh circuit 17.The time of integration, refresh circuit 17 exported time T1 to counter circuit 14 and counting circuit 15.Counting circuit 15 exports the measurement result S3 of Van to memory circuit 18.

Note that in the semiconductor device 1 shown in Fig. 1, a configuration Just One Of Those Things example of integrator 12 and comparator 13, and other can be adopted as an alternative to connect.Such as, although integrator 12 and comparator 13 are connected to ground GND respectively, they not necessarily can be connected to ground.Therefore, benchmark voltage is also not limited to 0V.

The more new description > of < time T1

Next, the details of the renewal of the time T1 undertaken by refresh circuit 17 time of integration will be described.Note that in the following description, the time T1 in the N time A/D conversion in semiconductor device 1 is set to T1_N, and the N time A/D in semiconductor device 1 change in time T2 be set to T2_N.In addition, semiconductor device 1 should be standardized to terminate the integration for an A/D conversion in intended conversion cycle T conv.

Refresh circuit 17 received time T2_N the N time conversion, upgrades the time T1_N in changing for the N time and was exported to counter circuit 14 and counting circuit 15 as the time T1_ (N+1) in (N+1) secondary conversion from counter circuit 14 time of integration.In addition, counter circuit 14 counts as the time T1_ (N+1) by the time T1 that the time of integration, refresh circuit 17 upgraded when the counting of (N+1) secondary conversion.

Therefore, integrator 12 when (N+1) secondary conversion by analog signal Van integration until time T1_ (N+1).In addition, counting circuit 15 utilizes the calculating performing above-mentioned formula (4) as the T1_ (N+1) by the time T1 that the time of integration, refresh circuit 17 upgraded in the calculating of (N+1) secondary conversion.

The time of integration refresh circuit 17 by according in the N time conversion during intended conversion cycle T conv not yet cost carry out T1 update time for time T1 when extending remaining time of integration (N+1) secondary conversion.Particularly, the time of integration, refresh circuit 17 such as performed the calculating illustrated hereinafter, and exported the time T1_ (N+1) in (N+1) secondary conversion.

The time of integration, refresh circuit 17 calculated the formula (6) met below, i.e. the time coefficient α _ N of formula (7).

(T1_N+T2_N)×α_N≤Tconv'…(6)

α_N≤Tconv'/(T1_N+T2_N)…(7)

But Tconv' meets lower relation of plane.

Tconv'＝Tconv－Tmargin…(8)

Here, the surplus cycle is for terminating the predetermined period changed in change-over period Tconv, even if time T2_ (N+1) becomes longer than time T2_N due to the change in voltage of the analog signal Van between the N time conversion and (N+1) secondary conversion.As mentioned above, the time of integration, refresh circuit 17 carried out T1 update time based on the time span in the cycle obtained by being got rid of from change-over period Tconv by predetermined surplus cycle T margin.But Tmargin can be 0.Therefore, as shown in formula (6) or (7), time when supposing integrator 12 in (N+1) secondary conversion by the analog signal Van integration of voltage identical for the voltage in changing with the N time, time coefficient α _ N can be described as and indicates that terminate in predetermined period under the condition of integration can the coefficient of how time expand T1.

The time of integration, refresh circuit 17 such as calculated Tconv'/(T1_N+T2_N), as the α _ N meeting above-mentioned formula (7).

Next, the time of integration, refresh circuit 17 formula (9) passed through below calculated the time T1_ (N+1) as (N+1) secondary time T1.

T1_(N+1)＝α_N×T1_N…(9)

Here, when analog signal Van does not change between the N time conversion and (N+1) secondary conversion, formula (10) is below set up.

T1_(N+1)+T2_(N+1)＝(T1_N+T2_N)×α_N…(10)

Therefore, from the formula (11) below above-mentioned formula (6) and (10) illustrate.

T1_(N+1)+T2_(N+1)≤Tconv'＜Tconv…(11)

For this reason, can complete in intended conversion cycle T conv the time of integration of (N+1) secondary conversion.In addition, even if analog signal Van has minor variations between the N time conversion with (N+1) secondary conversion, the increase of the time of integration that time of integration of (N+1) secondary conversion also can be caused due to the change of analog signal by absorption by means of surplus cycle T margin and completing in intended conversion cycle T conv.In this case, such as, the value of calculating that hypothesis can only be set as refresh circuit 17 time of integration at the surplus cycle T margin of change of the analog signal Van to change between (N+1) secondary conversion for the N time is corresponded to.

Note that the time of integration, refresh circuit 17 such as exported predetermined initial value to counter circuit 14 as the T1_1 of the T1 being used for first time conversion.Predetermined initial value can be identical with according to the time T1 used in the semiconductor device 9 of comparative example.

The explanation > of the operation of < semiconductor device 1

Next, the operation according to the semiconductor device 1 of embodiment 1 will be described.Fig. 2 is the time diagram of the operation that semiconductor device 1 is shown.Note that in fig. 2, stand-by period Tinterval is to the stand-by period performing next A/D conversion in the A/D conversion repeated.But waiting time can be 0.

First, at time t0 place, the switching over signal S1 exporting control circuit 16 from counter circuit 14 to becomes high level.As its result, the switch 10 of analog signal Van side connected by control circuit 16, and disconnects the switch 11 of integration reference voltage V ref side.Integrator 12 is by analog signal Van integration to be entered.

Counter circuit 14 performs counting operation according to the time T1 that refresh circuit 17 exports from the time of integration.Note that the T1_1 of the time T1 as first time conversion is predetermined initial value.

At time t1 place, the count value of counter circuit 14 becomes the value identical with T1_1.At time t1 place, the switching over signal S1 exporting control circuit 16 from counter circuit 14 to becomes low level.As its result, control circuit 16 disconnects the switch 10 of analog signal Van side, and connects the switch 11 of integration reference voltage V ref side.

Integrator 12 is by integration reference voltage V ref integration to be entered.The output of integrator 12 and benchmark voltage (0V) compare by comparator 13, and export comparator output signal S2 to counter circuit 14.Note that the comparator output signal S2 exported by comparator 13 is high level, until the output of integrator 12 reaches benchmark voltage, and become low level when the output of integrator 12 reaches benchmark voltage.

Counter circuit 14 counts until comparator output signal S2 becomes low level time T2_1 from time t1.

At time t2 place, comparator output signal S2 becomes low level.Counter circuit 14 time T2_1 is exported to counting circuit 15 and the time of integration refresh circuit 17.

When time T2_1 exports from counter circuit 14, counting circuit 15 utilizes time T1_1 and T2_1 to perform the calculating of above-mentioned formula (4), and exports result of calculation to memory circuit 18.As its result, memory circuit 18 stores the measurement result of the analog signal Van of first time conversion.

Meanwhile, when time T2_1 exports from counter circuit 14, the time of integration, refresh circuit 17 calculated time coefficient α _ 1, and calculated time T1_2 further from time coefficient α _ 1.The time of integration, refresh circuit 17 exported the time T1_2 calculated to counter circuit 14 and counting circuit 15.

At time t3 place, the change-over period Tconv in first time A/D conversion terminates.In addition, at time t4 place, after the stand-by period Tinterval changed to next A/D, start second time A/D conversion.In second time A/D conversion, utilize as the integration performed by the time T1 that the time of integration, refresh circuit 17 upgraded analog signal Van, to the calculating of result of analog signal Van and the calculating of the time T1_3 in changing third time A/D of measuring second time conversion.

After this, repeat A/D conversion similarly.As mentioned above, (N+1) secondary A/D conversion utilizes the time T1 calculated by refresh circuit 17 time of integration when the N time A/D changes to perform.When doing like this, as shown in Figure 2, the time being performed integration by integrator 12 terminates in each A/D conversion in change-over period Tconv.

The explanation > of < time of integration

Fig. 3 is the figure of the difference of the time of integration at each electromotive force for analog signal Van illustrated in semiconductor device 1.Please note, in figure shown in Figure 3, dotted line represents that the integration when the analog signal Van of maximum electrical potential is input to integrator 12 exports, solid line represents that integration when the analog signal Van of minimum potential is input to integrator 12 exports, and the integration when analog signal Van of electromotive force that chain-dotted line represents between maximum electrical potential and minimum potential is input to integrator 12 exports.

As shown in Figure 3, although in first time conversion, the T1_1 time of integration of analog signal Van is even constant relative to the analog signal Van of any electromotive force, after second time conversion, the electromotive force of analog signal Van is lower, and the T1 time of integration of analog signal Van is longer.In addition, after second time conversion, analog signal Van is substantially equal with the total mark time of integration reference voltage V ref, and regardless of analog signal Van electromotive force how.As mentioned above, semiconductor device 1 performs by integrator 12 time that integration grows as far as possible in change-over period Tconv, and no matter the electromotive force of analog signal Van is how.

The explanation > of < transformed error

Fig. 4 A and Fig. 4 B is the transformed error that the figure of the transformed error that A/D converter is shown, Fig. 4 A show the semiconductor device 9 according to above-mentioned comparative example, and Fig. 4 B shows the transformed error of the semiconductor device 1 according to the present embodiment.Go out as shown in Figure 4 A and 4 B, semiconductor device 1 according to the present embodiment has such conversion accuracy, this conversion accuracy is compared with the conversion accuracy of the semiconductor device 9 according to comparative example, and the electromotive force along with analog signal Van becomes lower and improves more.

According to semiconductor device 1 T1 update time of the present embodiment, so as mentioned above according in the N time conversion during intended conversion cycle T conv not yet cost for extending remaining time of integration time T1 during (N+1) secondary conversion.For this reason, with compared with the semiconductor device 9 of comparative example, semiconductor device 1 can use change-over period Tconv more effectively.

When analog signal Van is by semiconductor device 9 integration according to comparative example, be constant to the quantity of the clock that analog signal Van samples, because be constant the time of integration of analog signal Van, and no matter the electromotive force of analog signal is how.By comparison, according in the semiconductor device 1 of the present embodiment, the time of integration of analog signal Van is set in the scope being no more than change-over period Tconv the time of integration of analog signal Van and integration reference voltage V ref long as much as possible.For this reason, according in the semiconductor device 1 of the present embodiment, the electromotive force of analog signal Van is lower, becomes the time of integration longer.In addition, the time of integration along with analog signal Van becomes longer, increases, and therefore can improve the conversion accuracy of analog-digital conversion to the quantity of the clock that analog signal Van samples.Especially, when the electromotive force of analog signal Van is lower, the quantity of the clock that analog signal Van samples is increased significantly, and therefore can improve the conversion accuracy of analog-digital conversion significantly.

< embodiment 2>

Next, the onboard system of the semiconductor device used as described in Example 1 is described as embodiment 2.

Fig. 5 illustrates the schematic diagram be provided with the configuration of the vehicle 2 of the onboard system 3 mentioned later.Vehicle 2 comprises: engine 20; Detecting unit 21; Decelerator 22; Driving shaft 23; Driving wheel 24; With ECU (electronic control unit) 25.

Vehicle 2 is advanced by the rotation of driving wheel 24 by means of the actuating force from engine 20.

Engine 20 combustion fuel, and the energy obtained by combustion fuel is transferred to driving shaft 23 by decelerator 22.

In the present embodiment, detecting unit 21 be detect vehicle 2 state and detect the transducer of the state relevant with engine 20.More specifically, the suction temperature, exhaust temperature, engine cooling water temperature etc. of detecting unit 21 detecting and alarm 20.Detecting unit 21 exports the status signal S10 detected to ECU25.

ECU25 generates based on the state detected by detecting unit 21 the control signal S11 controlled engine 20, and exports control signal S11 to engine 20.Engine 20 operates based on the control signal S11 exported by ECU25.Such as, engine 20 operates according to based on the determined fuel injection amount of control signal S11, ignition timing etc.

The explanation > of the configuration of < onboard system 3

Fig. 6 is the block diagram of the summary of the configuration that onboard system 3 is shown.Onboard system 3 has detecting unit 21 above-mentioned and ECU25.Onboard system 3 measures the state value of the state of instruction vehicle 2, and controls vehicle 2 based on the state value measured.Particularly, onboard system 3 measures the temperature of engine 20, and controls engine 20 based on the temperature measured.

ECU25 has MCU26 and sensor interface unit (transducer I/F unit) 27.MCU26 is the microcontroller (control unit) comprising central processing circuit (processor unit), memory cell etc., and performs generation of the control signal S11 controlling engine 20 etc.

Transducer I/F unit 27 is semiconductor devices that the analog signal input comprising in the future Autonomous test unit 21 converts the A/D converter of digital value to.That is, transducer I/F unit 27 performs the calculating of the digital value of the analog signal (status signal S10) of the testing result as detecting unit 21, and the state value of measuring vehicle 2.

MCU26 obtains the digital value of the state detected by detecting unit 21 from transducer I/F unit 27, and generates control signal S11.As mentioned above, MCU26 controls vehicle 2 based on the state value measured by transducer I/F unit 27.

Fig. 7 is the block diagram of the detailed configuration that onboard system 3 is shown.Detecting unit 21 is the transducers detecting the temperature relevant with engine, and has reference resistor 210 and thermistor 211.Here, the resistance of thermistor 211 such as changes according to engine breath temperature.By such configuration, detecting unit 21 exports the status signal S10 as analog signal (voltage) to ECU25 according to testing result.

Transducer I/F voltage 27 has the configuration of the semiconductor device 1 comprised according to embodiment 1.That is, transducer I/F unit 27 comprises: above-mentioned switch 10 and 11, integrator 12, comparator 13, counter circuit 14, counting circuit 15, control circuit 16, the time of integration refresh circuit 17 and memory circuit 18.In addition, transducer I/F voltage 27 has the reference voltage generation unit 270 generating integration reference voltage V ref further, and as SPI (Serial Peripheral Interface (SPI)) I/F271 for the communication interface of input and output data between memory circuit 18 and MCU26.In addition, a terminal of switch 10 is connected to the input of integrator 12, and its another terminal is connected to the output of detecting unit 21.In addition, a terminal of switch 11 is connected to the input of integrator 12, and its another terminal is connected to the output of reference voltage generation unit 270.

By above-described configuration, temperature, the A/D performed as the status signal S10 of the analog signal of the temperature detected by transducer I/F unit 27 of onboard system 3 detecting and alarm 20 in detecting unit 21 change and measure the temperature of engine 20 thus.The MCU26 of onboard system 3 then generates control signal S11 based on the temperature measured, and controls engine 20.

Here, the state execution for the vehicle gone out with analog signal detection by detecting unit 21 is changed with the A/D similar according to the semiconductor device 1 of above-described embodiment 1.Therefore, be set to time of integration of being undertaken by integrator 12 of the analog signal detected by detecting unit 21 in the scope being no more than change-over period Tconv the time of integration of analog signal and integration reference voltage V ref long as much as possible.For this reason, compared with being set to constant and electromotive force that is no matter analog signal how situation with time T1, the quantity of the clock of analog signal sampling being increased, and therefore can improve the conversion accuracy of analog-digital conversion.That is, the certainty of measurement of the state value of vehicle can be improved.Therefore, MCU26 wherein suppressed the state value of error to generate control signal S11 owing to utilizing, so can perform the accurate control of the state corresponding to vehicle 2.Particularly, MCU26 such as accurately can control the fuel injection amount, ignition timing etc. of engine 20 according to the state of engine 20.

Although note that the state of engine 20 is illustrated as the state of vehicle 2 in the description of the present embodiment, this is only an example.Such as, onboard system 3 can measure the state of decelerator 22, brake (not shown) and vehicle air conditioning (not shown) to replace engine 20, and can control them based on measurement result.In addition, measured object is not limited to temperature, and can be such as Fluid Volume, weight etc.

< embodiment 3>

Next, embodiment 3 will be described.

According in the semiconductor device 1 of embodiment 1, the input of control circuit 16 pairs of integrators 12 controls to make integrator 12 perform the integration of analog signal Van and integration reference voltage V ref once in intended conversion cycle T conv, and the time of integration, refresh circuit 17 upgraded the time T1 in next change-over period Tconv based on the time T2 in current change-over period Tconv.That is, in semiconductor device 1, in the A/D conversion repeated, the time T1 of (N+1) secondary A/D conversion decides based on time T2 during the N time A/D conversion.

By comparison, according in the semiconductor device 4 of embodiment 3, the input of control circuit 16 pairs of integrators 12 controls to make integrator 12 in intended conversion cycle T conv, perform the integration twice of analog signal Van and integration reference voltage V ref, and the refresh circuit 42 time of integration mentioned later to be upgraded the second time T1 in change-over period Tconv based on the very first time T2 in change-over period Tconv.That is, in semiconductor device 4, in a change-over period Tconv, calculate time T1, and the time T1 of utilization in change-over period Tconv is by analog signal Van integration.

Particularly, change-over period Tconv is divided into pre-integration cycle T pre and main integration period Tmain by the semiconductor device 4 according to embodiment 3, and by analog signal Van integration in each in these integration periods.That is, semiconductor device 4 first in pre-integration cycle T pre by analog signal Van and integration reference voltage V ref integration, and also in main integration period Tmain subsequently by analog signal Van and integration reference voltage V ref integration.Here, semiconductor device 4 utilizes the integral result in pre-integration cycle T pre to decide the time of integration of the analog signal Van in main integration period Tmain.

< is according to the explanation > of the configuration of the semiconductor device of embodiment 3

Fig. 8 is the circuit diagram of the configuration of the semiconductor device 4 illustrated according to embodiment 3.Semiconductor device 4 is following biproduct somatotype A/D converters, has: switch 10 and 11; Integrator 12; Comparator 13; Control circuit 16; Counter circuit 40; Counting circuit 41; The time of integration refresh circuit 42; Integral mode commutation circuit 43; With memory circuit 18.

As mentioned above, semiconductor device 4 is with the difference of embodiment 1: with counter circuit 40, counting circuit 41 and the time of integration refresh circuit 42 replace respectively the counter circuit 14 of the semiconductor device 1 according to embodiment 1, counting circuit 15 and the time of integration refresh circuit 17, and with the addition of integral mode commutation circuit 43.Although note that the configuration that also illustrate that in the present embodiment and provide memory circuit 18, semiconductor device 4 does not need necessarily to store result of calculation.Therefore, when semiconductor device 4 does not store result of calculation, do not need to provide memory circuit 18.

Hereinafter, semiconductor device 4 and the difference according to the semiconductor device 1 of embodiment 1 will be described.

Integral mode commutation circuit 43 switches pre-integration cycle T pre and main integration period Tmain in a change-over period Tconv.Particularly, the cycle obtained by getting rid of above-mentioned surplus cycle T margin from intended conversion cycle T conv is divided into pre-integration cycle T pre and main integration period Tmain by integral mode commutation circuit 43.But pre-integration cycle T pre is the cycle shorter than main integration period Tmain.According in the semiconductor device 4 of the present embodiment, be perform in pre-integration cycle T pre for calculating the integration of time T1 when A/D changes, and actual A/D conversion performs in main integration period Tmain.Therefore, main integration period Tmain is preferably long as much as possible relative to pre-integration cycle T pre, to guarantee the quantity of the sampling when A/D changes.For this reason, as shown in formula (12) below, pre-integration cycle T pre is preferably enough short than main integration period Tmain.

The main integration period Tmain of pre-integration cycle T pre<< ... (12)

Integral mode commutation circuit 43 exports the signal of instruction pre-integration cycle T pre to counter circuit 40 when the change-over period, Tconv started.In addition, at the end of pre-integration cycle T pre, integral mode commutation circuit 43 exports the signal of the main integration period Tmain of instruction to counter circuit 40.

With counter circuit 14 similarly, counter circuit 40 couples of time T1 and T2 count.But counter circuit 40 counts time T1 and T2 in pre-integration cycle T pre based on the signal from integral mode commutation circuit 43, and subsequently, also in main integration period Tmain, time T1 and T2 is counted.Therefore, counter circuit 40 counts twice time T1 and T2 in a change-over period Tconv.Note that counter circuit 40 counts the T1 specified by refresh circuit 42 time of integration.

The time of integration, refresh circuit 42 was the circuit carrying out T1 update time based on the time T2 of the pre-integration cycle T pre counted by counter circuit 40.More specifically, the time of integration, refresh circuit 42 calculated the time T1 counted by counter circuit 40 in main integration period Tmain based on the time T2 of pre-integration cycle T pre.The time T2 of the pre-integration cycle T pre counted by counter circuit 40 is input to refresh circuit 42 time of integration.In addition, the time of integration refresh circuit 42 output, the time T1 namely used in main integration period Tmain is input to counter circuit 40 and counting circuit 41.In addition, the time of integration, refresh circuit 42 exported the time T1 of pre-integration cycle T pre to counter circuit 40.

The explanation > of the renewal of < time T1

Next, the details of the renewal of the time T1 undertaken by refresh circuit 42 time of integration will be described.Note that in the following description, each Reference numeral is defined as follows:

The time T1 of the pre-integration cycle T pre in Tp1_N: the N time conversion;

The time T2 of the pre-integration cycle T pre in Tp2_N: the N time conversion;

The time T1 of the main integration period Tmain in Tm1_N: the N time conversion; And

The time T2 of the main integration period Tmain in Tm2_N: the N time conversion.

Although note that Tp1_N is illustrated as fixed value and the quantity N no matter changed how, the present invention is not limited thereto.Such as, Tp1_N can be predetermined value different for each conversion.

Refresh circuit 42 received time Tp2_N the N time conversion, calculated the time Tm1_N in changing for the N time and exported to counter circuit 40 and counting circuit 41 from counter circuit 40 time of integration.The time of integration, refresh circuit 42 was according to carrying out update time T1 the time of integration (according to lacking of the time of integration) in pre-integration cycle T rpe so that time T1 when extending the conversion in main integration period Tmain.Particularly, such as, the time of integration, refresh circuit 42 performed the calculating illustrated hereinafter, and exported the time Tm1_N in main integration period Tmain.

The time of integration, refresh circuit 42 calculated the formula (13) met below, i.e. the time coefficient α _ N of formula (14).

(Tp1_N+Tp2_N)×α_N≤Tmain…(13)

α_N≤Tmain/(Tp1_N+Tp2_N)…(14)

But Tmain meets lower relation of plane.

Tmain＝Tconv－Tpre－Tmargin…(15)

Note that Tmargin can be 0.Therefore, as shown in formula (13) or (14), time coefficient α _ N can be described as that instruction terminates under the condition of integration in main integration period Tmain can the coefficient of how time expand T1.

The time of integration, refresh circuit 42 such as calculated Tmain/ (Tp1_N+Tp2_N) as the α _ N meeting above-mentioned formula (14).

Next, the time of integration, refresh circuit 42 was by the time Tm1_N of formula (16) calculating below as the time T1 in main integration period Tmain.

Tm1_N＝α_N×Tp1_N…(16)

Because change-over period Tconv is enough short compared with the speed of the change of analog signal Van, do not change so analog signal Van in a change-over period Tconv can be considered as.For this reason, the electromotive force of analog signal Van is substantially invariable in pre-integration cycle T pre and main integration period Tmain.Therefore, formula (17) is below established.

Tm1_N+Tm2_N＝(Tp1_N+Tp2_N)×α_N…(17)

As a result, from the formula (18) below above-mentioned formula (13) and (17) illustrate.

Tm1_N+Tm2_N≤Tmain＜Tconv…(18)

For this reason, complete in intended conversion cycle T conv the time of integration of the N time conversion.

The Tm1_N calculated by refresh circuit 42 time of integration and the Tm2_N counted by counter circuit 40 is input to counting circuit 41.Counting circuit 41 performs the calculating shown in formula (19) below, and exports A/D transformation result.

Van＝﹣Vref×(Tm2_N/Tm1_N)…(19)

The explanation > of the operation of < semiconductor device 4

Next, the operation according to the semiconductor device 4 of embodiment 3 will be described.Fig. 9 is the time diagram of the operation that the semiconductor device 4 when the N time conversion is shown.Note that in the following description, the device as the input and output below the signal performed as shown in Figure 8 and Figure 9 is described by semiconductor device 4.Control circuit 16 exports on/off signal SWVan to switch 10, and exports on/off signal SWVref to switch 11.Counter circuit 40 exports switching over signal S1 to control circuit 16.Comparator 13 exports comparator output signal S2 to counter circuit 40.The time Tp2 of the time T2 as pre-integration cycle T pre is exported to refresh circuit 42 time of integration by counter circuit 40, and exports the time Tm2 of the time T2 as main integration period Tmain to counting circuit 41.In addition, the time of integration, refresh circuit 42 exported the time Tp1 of the time T1 as pre-integration cycle T pre to counter circuit 40, and exported the time Tm1 of the time T1 as main integration period Tmain to counter circuit 40 and counting circuit 41.Counting circuit 41 exports the measurement result S3 of Van to memory circuit 18.Integral mode commutation circuit 43 exports integral mode switching signal S4 to counter circuit 40.

First, at the time t0 place of the time started as the N time conversion, the integral mode switching signal S4 exported from integral mode commutation circuit 43 becomes high level, and performs the integration of pre-integration cycle T pre.Particularly, perform below become with integral mode switching signal S4 the operation that high level is associated.The switching over signal S1 exporting control circuit 16 from counter circuit 40 to becomes high level.As its result, the switch 10 of analog signal Van side connected by control circuit 16, and disconnects the switch 11 of integration reference voltage V ref side.Integrator 12 is by analog signal Van integration to be entered.

Counter circuit 40 performs counting operation according to the time Tp1_N that refresh circuit 42 exports from the time of integration.

At time t1 place, the count value of counter circuit 40 becomes the value identical with Tp1_N.At time t1 place, the switching over signal S1 exporting control circuit 16 from counter circuit 40 to becomes low level.As its result, control circuit 16 disconnects the switch 10 of analog signal Van side, and connects the switch 11 of integration reference voltage V ref side.Integrator 12 is by integration reference voltage V ref integration to be entered.The output of integrator 12 and benchmark voltage (0V) compare by comparator 13, and export comparator output signal S2 to counter circuit 40.Note that the comparator output signal S2 exported by comparator 13 is high level, until the output of integrator 12 reaches benchmark voltage, and become low level when the output of integrator 12 reaches benchmark voltage.

Counter circuit 40 counts from time t1 time Tp2_N, until comparator output signal S2 becomes low level.

At time t2 place, comparator output signal S2 becomes low level.Time Tp2_N is exported to refresh circuit 42 time of integration by counter circuit 40.

When time Tp2_N exports from counter circuit 40, the time of integration, refresh circuit 42 calculated time coefficient α _ N, and calculated time Tm1_N further from time coefficient α _ N.The time of integration, refresh circuit 42 exported the time Tm1_N calculated to counter circuit 40 and counting circuit 41.

When pre-integration cycle T pre is at the end of time t3 place, the integral mode switching signal S4 exported from integral mode commutation circuit 43 becomes low level, and performs the integration of main integration period Tmain.Particularly, perform below become with integral mode switching signal S4 the operation that low level is associated.The switching over signal S1 exporting control circuit 16 from counter circuit 40 to becomes high level.As its result, the switch 10 of analog signal Van side connected by control circuit 16, and disconnects the switch 11 of integration reference voltage V ref side.Integrator 12 is by analog signal Van integration to be entered.

Counter circuit 40 performs counting operation according to the time Tm1_N that refresh circuit 42 exports from the time of integration.

At time t4 place, the count value of counter circuit 40 becomes the value identical with Tm1_N.At time t4 place, the switching over signal S1 exporting control circuit 16 from counter circuit 40 to becomes low level.As its result, control circuit 16 disconnects the switch 10 of analog signal Van side, and connects the switch 11 of integration reference voltage V ref side.Integrator 12 is by integration reference voltage V ref integration to be entered.The output of integrator 12 and benchmark voltage (0V) compare by comparator 13, and export comparator output signal S2 to counter circuit 40.

Counter circuit 40 counts from time t4 time Tm2_N, until comparator output signal S2 becomes low level.

At time t5 place, comparator output signal S2 becomes low level.Counter circuit 40 exports time Tm2_N to counting circuit 41.

When time Tm2_N exports from counter circuit 40, counting circuit 41 utilize from the time of integration time Tm2_N that refresh circuit 42 exports and time Tm1_N to perform the calculating of above-mentioned formula (19), and export result of calculation to memory circuit 18.As its result, memory circuit 18 stores the measurement result of the analog signal Van of the N time conversion.

At time t6 place, the change-over period Tconv in the N time A/D conversion terminates.In addition, at time t7 place, after the stand-by period Tinterval changed to (N+1) secondary A/D, start (N+1) secondary A/D conversion.According to mode so as mentioned above, semiconductor device 4 repeats A/D conversion.

The explanation > of the time of integration in < semiconductor device 4

Figure 10 is the figure of the difference of the time of integration illustrated according to each electromotive force for analog signal Van in the semiconductor device 4 of embodiment 3.Please note, in figure shown in Figure 10, dotted line represents that the integration when the analog signal Van of maximum electrical potential is input to integrator 12 exports, solid line represents that integration when the analog signal Van of minimum potential is input to integrator 12 exports, and the integration when analog signal Van of electromotive force that chain-dotted line represents between maximum electrical potential and minimum potential is input to integrator 12 exports.

As shown in Figure 10, although in the integration in pre-integration cycle T pre, the Tp1_N time of integration of analog signal Van is constant relative to the analog signal Van of any electromotive force, but in the integration in main integration period Tmain, the electromotive force of analog signal Van is lower, and the Tm1_N time of integration of analog signal Van is longer.In addition, in main integration period Tmain, analog signal Van is substantially equal with the total mark time of integration reference voltage V ref, and no matter the electromotive force of analog signal Van is how.As mentioned above, semiconductor device 4 performs by integrator 12 time that integration grows as far as possible in main integration period Tmain, and no matter the electromotive force of analog signal Van is how.

According to semiconductor device 4 T1 update time of the present embodiment, so that as mentioned above according to the time T1 during conversion extended the time of integration in pre-integration cycle T pre in main integration period Tmain.Namely, according in the semiconductor device 4 of the present embodiment, the time of integration of the analog signal Van in main integration period Tmain is set in the scope that the time of integration of analog signal Van and integration reference voltage V ref is no more than main integration period Tmain long as much as possible.For this reason, according in the semiconductor device 4 of the present embodiment, the electromotive force of analog signal Van is lower, and the time of integration in main integration period Tmain becomes longer.In addition, the time of integration along with analog signal Van becomes longer, also increases the quantity of the clock that analog signal Van samples, and therefore can improve the conversion accuracy of analog-digital conversion.Especially, when the electromotive force of analog signal Van is lower, the quantity of the clock that analog signal Van samples is increased significantly, and therefore can improve the conversion accuracy of analog-digital conversion significantly.

In addition, according to the semiconductor device 4 of embodiment 3, there is further advantage below.According in the semiconductor device 1 of embodiment 1, have employed the configuration wherein can expecting to improve conversion accuracy in second time or the conversion of A/D below.By comparison, according in the semiconductor device 4 of embodiment 3, due to analog signal Van the time of integration T1 calculating and time of integration T1 in integration perform in a change-over period Tconv, so raising conversion accuracy just can be expected from first time A/D conversion.

In addition, according in the semiconductor device 1 of embodiment 1, even if there occurs the change of analog signal Van during the stand-by period Tinterval changed to next A/D, because the existence of surplus cycle T margin, the time of integration also can not exceed change-over period Tconv.But when the change of analog signal Van is greater than the change corresponding to the setting surplus cycle T margin in semiconductor device 1, integration may can not terminate in change-over period Tconv.By comparison, according in the semiconductor device 4 of embodiment 3, the electromotive force substantial constant in a change-over period Tconv as mentioned above of analog signal Van.Therefore, according to the semiconductor device 4 of embodiment 3, integration can terminate during change-over period Tconv and no matter during stand-by period Tinternval in the presence/absence of the change of analog signal Van.

< embodiment 4>

Next, the onboard system 5 of the semiconductor device used as described in Example 3 is described as embodiment 4.Note that the onboard system be mounted according to the onboard system of the present embodiment in vehicle 2 above-mentioned, and below some is different from the onboard system 3 shown in embodiment 2.Hereinafter, by illustrate this different from the onboard system 3 shown in Fig. 2 some, and will to omit and about the explanation of the similar configuration of the configuration of the onboard system 3 shown in Fig. 2.

The explanation > of the configuration of < onboard system 5

The block diagram of the detailed configuration of onboard system 5 is shown during Figure 11.As shown in figure 11, according in the onboard system 5 of the present embodiment, respectively, replace detecting unit 21 with detecting unit 50, and replace transducer I/F unit 27 with transducer I/F unit 51.

Different with detecting unit 21, detecting unit 50 comprises the multiple transducers detecting the temperature relevant with engine.Particularly, detecting unit 50 has reference resistor 500 and thermistor 501_1 to 501_n (but, be not less than the integer of 2 during n).Here, the detected object of thermistor 501_1 to 501_n is different respectively.Such as, the suction temperature of thermistor 501_1 detecting and alarm 20, thermistor 501_2 detector exhaust temperature, and 501_n detects its engine cooling water temperature.In addition, switch 502_1 to 502_n is connected to corresponding thermistor 501_1 to 501_n.Detecting unit 50 detects the temperature as the detected object of the thermistor of any switch connected by the control of MCU26 be connected among switch 502_1 to 502_n.

Although have the configuration of the semiconductor device 1 comprised according to embodiment 1 according to the transducer I/F unit 27 of embodiment 2, transducer I/F unit 51 has the configuration of the semiconductor device 4 comprised according to embodiment 3.That is, transducer I/F unit 51 comprises: switch 10 and 11 above-mentioned, integrator 12, comparator 13, counter circuit 40, counting circuit 41, control circuit 16, the time of integration refresh circuit 42, integral mode commutation circuit 43 and memory circuit 18.In addition, similar with the transducer I/F unit 27 according to embodiment 2, transducer I/F unit 51 has reference voltage generating circuit 270 and SPII/F271.

Switch 502_1 to 502_n controls as connecting along this place by MCU26.Now, when any one in turn on-switch 502_1 to 502_n, MCU26 disconnects other switches.In addition, MCU26 repeats this control to switch 502_1 to 502_n.Therefore, corresponding switch 502_1 to 502_n is periodically switched on.

As a result, the analog signal of the detected object sequentially selected is input to transducer I/F unit 51.In addition, transducer I/F unit 51 calculates the digital value of the analog signal of multiple detected object along this place.

The explanation > of the A/D conversion operations in < onboard system 5

Figure 12 is the time diagram that the A/D conversion performed by transducer I/F unit 51 is shown.Note that in fig. 12, for the purpose of simplifying the description, eliminate the diagram of surplus cycle T margin.As shown in figure 12, transducer I/F unit 51 performs A/D conversion to the input from thermistor 501_1 to 501_n along this place.Now, after the N time EOC of a certain thermistor and this thermistor is started next conversion before, perform the conversion to other thermistors.Such as, the N time conversion of thermistor 501_2 to 501_n is performed during the stand-by period Tinterval started to ensuing (N+1) secondary conversion after the N time EOC of thermistor 501_1.For this reason, suppose that the electromotive force inputted from the analog signal of thermistor 501_1 changes when the N time conversion and (N+1) secondary conversion.

But, owing to changing similar with the A/D by carrying out in the A/D performed by transducer I/F unit 51 changes according to the semiconductor device 4 of above-described embodiment 3, analog signal Van the time of integration T1 calculating and utilization perform in a change-over period Tconv, even if so there occurs the change of analog signal Van during stand-by period Tinterval, integration also can terminate during change-over period Tconv.

By such configuration, onboard system 5 detect in detecting unit 50 multiple detected object, perform detected by object analog signal A/D conversion and measure detected object thus.The MCU26 of onboard system 5 then generates control signal based on measurement result, and controls engine 20.

Here, according to the A/D conversion performed by transducer I/F unit 51, and change similar by the A/D performed according to the semiconductor device 4 of above-described embodiment 3, the conversion accuracy of analog-digital conversion can be improved.In addition, due to analog signal Van the time of integration T1 calculating and time of integration T1 in integration carry out in a change-over period Tconv, so can change from first time A/D the raising just expecting conversion accuracy.In addition, due to as mentioned above, even if there occurs the change of analog signal Van during stand-by period Tinterval, integration also can terminate during change-over period Tconv, so can be obtained the measurement result of multiple detected object by an A/D converter.This contributes to the size of onboard system and the reduction of cost.

As a result, according to onboard system 5, because the control signal controlling vehicle 2 can produce, so can perform the precision controlling of the state corresponding to vehicle 2 based on the high-precision measurement result of multiple state values of vehicle 2.In addition, due in doing so, the raising just expecting conversion accuracy can be changed, so the precision controlling of the state corresponding to vehicle 2 can be performed ahead of time from first time A/D.

Although note that temperature relevant with engine 20 in the explanation of embodiment is illustrated as the state of vehicle 2, this is only an example.Similar to Example 2, such as, onboard system 5 can measure the state of decelerator 22, brake (not shown) and vehicle air conditioning (not shown) to replace engine 20, and can control them based on measurement result.In addition, object to be measured is not limited to temperature, and can be such as Fluid Volume, weight etc.

Hereinbefore, although specifically illustrate the invention made by the present inventor based on embodiment, the invention is not restricted to already mentioned embodiment, and much less can make various change without departing from the scope of the invention.

Such as, although in example 2, transducer I/F unit 27 has been illustrated as the configuration with the semiconductor device 1 comprised according to embodiment 1, can adopt the configuration comprising and replace above according to the configuration of the semiconductor device 4 of embodiment 3.Similarly, although in example 4, transducer I/F unit 51 has been illustrated as the configuration with the semiconductor device 4 included according to embodiment 3, can adopt the configuration including and replace above according to the configuration of the semiconductor device 1 of embodiment 1.

Those skilled in the art can according to expectation by first to fourth embodiment combination.

Although the present invention is described with regard to several embodiment, those skilled in the art will recognize that, the present invention can utilize various modification to put into practice and the invention is not restricted to above-mentioned example in the spirit of claim of enclosing and scope.

In addition, the scope of claim is not restricted to the described embodiments.

In addition, note, applicant is intended to the equivalents containing all authority requirement key element, even if revise in course of the review below.

Claims (17)

1. a semiconductor device, comprising:

Integrator, repeats the first reference voltage integration after by analog signal integrator;

Comparator, compares the output of described integrator and the second reference voltage;

Counter circuit, is counted the first integral time of described analog signal integrator and second integral time of reaching described second reference voltage to the described output of described integrator from the integration of described first reference voltage determining;

Counting circuit, based on the digital value of analog signal described in described first integral time and described second integral Time Calculation;

Control circuit, perform control and make when described counter circuit counted the described first integral time, described analog signal is input to described integrator; And

The time of integration, refresh circuit, upgraded the described first integral time counted by described counter circuit based on the described second integral time counted by described counter circuit.

2. semiconductor device according to claim 1, wherein

The input that described control circuit controls described integrator makes described integrator within the intended conversion cycle by analog signal and the first reference voltage integration once, and

Described time of integration, refresh circuit upgraded the described first integral time in next change-over period based on the described second integral cycle in the current change-over period.

3. semiconductor device according to claim 1, wherein

The input that described control circuit controls described integrator makes described integrator by analog signal and the first reference voltage integration twice within the intended conversion cycle, and

Described time of integration, refresh circuit upgraded second the described first integral time in the described change-over period based on the described second integral time of first in the described change-over period.

4. semiconductor device according to claim 2, wherein said time of integration, refresh circuit upgraded the described first integral cycle based on the time span in the cycle obtained by getting rid of the predetermined surplus cycle from the described change-over period.

5. an analog-digital conversion method of solid, comprising:

For the first integral time by analog signal integrator after, by the first reference voltage integration;

The second integral time reaching the second reference voltage to integral result described integration from described first reference voltage is counted;

The described first integral time is upgraded based on the counted described second integral time;

For the upgraded described first integral time by analog signal integrator after, by described first reference voltage integration;

For the upgraded described first integral time by analog signal integrator after, the described second integral time is counted; And

Based on the upgraded described first integral time and for the upgraded described first integral time by the described second integral time after analog signal integrator, calculate the digital value of described analog signal.

6. analog-digital conversion method of solid according to claim 5, comprises further:

Within the intended conversion cycle by analog signal and the first reference voltage integration once; And

The described first integral time in next change-over period is upgraded based on the described second integral time in the current change-over period.

7. analog-digital conversion method of solid according to claim 5, comprises further:

By analog signal and the first reference voltage integration twice within the intended conversion cycle; And

Second the described first integral time in the described change-over period is upgraded based on the described second integral time of first in the described change-over period.

8. analog-digital conversion method of solid according to claim 6, the time span comprised further based on the cycle obtained by getting rid of the predetermined surplus cycle from the described change-over period upgrades the described first integral time.

9. an onboard system, comprising:

Detecting unit, detects the state of vehicle;

Semiconductor device, is calculated the digital value as the analog signal of the testing result obtained by described detecting unit and measures the state value of described vehicle;

Control unit, controls described vehicle based on the described state value measured by described semiconductor device,

Wherein said semiconductor device comprises:

Integrator, repeats the first reference voltage integration after by the described analog signal integrator from described detecting unit;

Comparator, compares the output of described integrator and the second reference voltage;

Counter circuit, is counted the first integral time of described analog signal integrator and second integral time of reaching described second reference voltage to the described output of described integrator from the integration of described first reference voltage determining;

Counting circuit, based on the digital value of analog signal described in described first integral time and described second integral Time Calculation;

Control circuit, perform control and make when described counter circuit counted the described first integral time, described analog signal is input to described integrator; And

The time of integration, refresh circuit, upgraded the described first integral time counted by described counter circuit based on the described second integral time counted by described counter circuit.

10. onboard system according to claim 9, wherein

Described detecting unit detects multiple detected object,

The analog signal of the detected object sequentially selected is input to described semiconductor device, and

Described semiconductor device sequentially calculates the digital value of the described analog signal of described multiple detected object.

11. onboard systems according to claim 9, wherein

The input that described control circuit controls described integrator makes described integrator within the intended conversion cycle by analog signal and the first reference voltage integration once, and

Described time of integration, refresh circuit upgraded the described first integral time in next change-over period based on the described second integral time in the current change-over period.

12. onboard systems according to claim 9, wherein

The input that described control circuit controls described integrator makes described integrator by analog signal and the first reference voltage integration twice within the intended conversion cycle, and

Described second described first integral cycle that the time of integration, refresh circuit upgraded within the described change-over period based on the described second integral cycle of first in the described change-over period.

13. onboard systems according to claim 11, wherein said time of integration, refresh circuit upgraded the described first integral time based on the time span in the cycle obtained by getting rid of the predetermined surplus cycle from the described change-over period.

14. 1 kinds of method of measurement, comprising:

Detect the state as the vehicle of analog signal;

For the first integral time by after the described analog signal integrator that detects, by the first reference voltage integration;

The second integral time reaching the second reference voltage to integral result integration from described first reference voltage is counted;

The described first integral time is upgraded based on the counted described second integral time;

For the upgraded described first integral time by after the analog signal integrator that newly upgrades, by described first reference voltage integration;

After the analog signal integrator that will newly detect, the described second integral time is counted; And

Based on upgraded described first integral time and the digital value in the described analog signal described second integral Time Calculation after described analog signal integrator newly detected, and measure the state value of described vehicle.

15. method of measurement according to claim 14, comprise further:

Within the intended conversion cycle by analog signal and the first reference voltage integration once; And

The described first integral time in next change-over period is upgraded based on the described second integral time in the current change-over period.

16. method of measurement according to claim 14, comprise further:

By analog signal and the first reference voltage integration twice within the intended conversion cycle; And

Second the described first integral time in the described change-over period is upgraded based on the described second integral time of first in the described change-over period.

17. method of measurement according to claim 15, the time span comprising the cycle obtained by getting rid of the predetermined surplus cycle from the described change-over period further upgrades the described first integral cycle.