JPH0754911B2 - A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of use) The present invention relates to a double integration type A / D converter, and more specifically to an A / D converter capable of achieving high resolution without impairing the response speed. Regarding D converter.

(Prior Art) FIG. 8 is a configuration block diagram of a conventionally known double integral A / D converter. In the figure, S1 is a switch that switches between the input analog signal Ex and the reference signal Es and extracts it, and INT is an integrator that integrates the signal extracted by the switch S1, and is connected in parallel with the resistor R, the capacitor C, the amplifier A, and the capacitor C. The switch S2 has been configured.

CP is a comparator that compares the output of the integrator with the common potential,
OS controls the on / off of switches S1 and S2 with a clock oscillator. CU is a counter that counts clocks and a comparator
The signal from CP controls the counting operation. DS is a display that displays the output of the counter.

The switch S1 first inputs the input signal Ex to the integrator INT for a fixed time Ts as shown in FIG. This causes the output of the integrator INT to change as shown in Fig. 10, and T
The integrator output Eo after s is expressed by equation (1).

Eo = {-Ex / (C · R)} · Ts (1) Next, the switch S1 inputs the reference voltage Es to the integrator INT as shown in FIG.

FIG. 10 is a diagram showing changes in the output voltage Eo of the integrator INT, and the integrator output Eo at this time is expressed by the equation (2).

Eo = {-Ex / (C · R)} · Ts + {Es / (C · R)} · t (2) Here, when the time until the output voltage Eo becomes zero is Tx,
Expression (3) is obtained.

Ex = (Tx / Ts) · Es (3) Therefore, if the integration time Ts and the reference voltage Es are constant, the input signal Ex is the output voltage after Tx, that is, the switch S1 is connected to the reference voltage Es side. By counting the time until Eo becomes zero with the counter CU, the analog signal input to the counter is input.
It is possible to obtain a digital signal compatible with Ex.

(Problems to be Solved by the Invention) The A / D converter having such a configuration is characterized in that the drift of the integration constant CR and the clock frequency does not cause an error.
However, in order to improve the accuracy of A / D conversion, it is necessary to increase the clock frequency or lengthen the integration time.

Here, there is a problem that a high-frequency circuit component must be used when the clock frequency is increased, and a response characteristic is deteriorated when the integration time is lengthened.

The present invention has been made in view of such problems,
The purpose is high resolution A / D without spoiling the response characteristics.
It is to realize the converter with a simple configuration.

(Means for Solving the Problems) FIG. 1 is a basic configuration block diagram of the present invention. In the figure, 1 is an integrator, 2 is a reference power supply, 3 is a preliminary integration power supply having a predetermined value, 4 is an input analog signal Ex to be converted into a digital signal, a reference voltage ± Es, and a preliminary power supply signal Eb are selected. This is a switch circuit that inputs to the integrator 1. Reference numeral 5 is a comparator having the output of the integrator 1 as input, 6 is counting means for inputting the signal from the comparator 5, and 7 is an arithmetic processing circuit for inputting the count value from the counting means 6 and performing average arithmetic processing. is there. Reference numeral 8 is a control means for inputting the signal from the comparator 5 and controlling the switch circuit 4, the integrator 1, and the counting means 6.

(Operation) The control means 8 controls the switch circuit 4, first selects the preliminary signal (Eb), applies the preliminary signal to the integrator 1 to perform the preliminary integration operation, and then the input analog signal ( E
x) and the reference signal (± Es) are sequentially selected and applied to the integrator 1 to perform the double integration operation. Thereafter, the AD conversion operation including the preliminary integration operation and the double integration operation is performed. T
1) is within the time from 1 pulse of the counting pulse to N pulses (1 / N is the ratio of the integrated current I1 at the time of pre-integration operation and the integrated current I4 at the time of inverse integration operation for integrating the reference signal). Then, the arithmetic processing means repeatedly performs the averaging of the count values obtained by the counting means by the AD conversion operation that is repeatedly performed, A digital signal corresponding to an analog signal is obtained.

Note that the sequence ai consists of n elements consisting of numerical values of 1,2,3, ... i ..., n, and is repeated as a1, a2, ... an, a1, a2 ,.

, The sequence ai is large with respect to its central value (n + 1) / 2,
They are arranged so that they are small, large, small, large, small ...

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a configuration block diagram showing an embodiment of the present invention. In the figure, those corresponding to the respective parts in FIG.
The same reference numerals are given. The integrator 1 is an operational amplifier OP1,
It is composed of a capacitor C and resistors R3 to R6. The reference voltage source 2 outputs a reference voltage ± Es, and the preliminary integration power supply 3 uses a reference voltage −Es divided by resistors R1 and R2. Reference numeral 9 denotes a microprocessor which internally includes a counter 6 as a counting means, and operates as the arithmetic processing means 7 and the control means 8 in FIG. The microprocessor 9 has a clock source in addition to the counter 6.
91, an output port 92 that operates in synchronization with the clock from the clock source 91, an arithmetic control unit (CPU) 93, and a memory 94.

The operation of the device configured as described above will be described below.

FIG. 3 is an operation waveform diagram showing an example of the operation. Here, it is assumed that the basic resolution is increased four times, and the resistances R1 and R2 and the integration resistances R4 and R5 that compose the preliminary integration power supply have a relationship as shown in equations (1) to (3). Has become.

R1 / (R1 + R2) = 1/4 (R1: R2 = 3: 1) …… (1) R1 << R5, R2 << R5 …… (2) R4 ＝ R5 …… (3) In Figure 3, To is Initial state, switch circuit 4
Switch S0 is turned on as shown in (a),
The capacitor C of the integrator 1 is short-circuited. In this state, the output voltage eA of the integrator is almost 0V, and the output voltage eA of the comparator 5 is
B depends on the offset voltage of the operational amplifier OP1 and the comparator 5, and both H and L levels are uncertain.

T1 is a preliminary integration period for increasing the resolution, which is a feature of the present invention. During this period, the switch S3 is turned on and the signal I1 from the preliminary integration power supply 3 is integrated. The integrated current value I1 here is expressed by equation (4).

I1 = {R2 / (R1 + R2)} x (-Es / R5) = (1/4) x (-Es / R5) = (1/4) x I4 (4) Also, the integration period T1 is a count. It is controlled by the microprocessor 9 according to a predetermined sequence so as to be evenly distributed in time series in any one of 1 to 4 clocks of the pulse (clock of the clock source 91). Details of this point will be described later.

T2 is another preliminary integration time, which is not directly related to the present invention, but by providing this section, AD conversion is possible even when the input analog signal Ex has a negative value. In this preliminary integration period, the switch S1 is on as shown in (b),
The integrator 1 integrates the charge amount shown in the equation (5) during that period.

I2 × T2 = (Es / R3) × T2 (5) In the next period T3, the input that cancels this charge amount is a negative input, and the negative input corresponds to the lower end of the input range of AD conversion.

T3 is the input integration interval. In this section, switch S4
Is turned on as shown in (e), and the current I3 proportional to the input analog signal is integrated for a certain time through the resistor R6.

T4 is an inverse integration section. In this section, the switch S2 is turned on as shown in (c), and the constant current value I4 represented by the equation (6) is inversely integrated.

I4 = -Es / R4 (6) The operations of the input integration section T3 and the inverse integration section T4 are the operations of a general double integration circuit, and are the same as those of the conventional device shown in FIG. Is.

The comparator 5 outputs the output voltage eA of the integrator 1 as shown in (f).
And the reference potential are compared and amplified, and as shown in (g), H / L
The digital signal eB is input to the microprocessor 9.
The microprocessor 9 receives the signal from the comparator 5 and receives T0
The timing signal of ~ T4 is generated, the switch circuit 4 is operated, and the output eB of the comparator 5 becomes high from the start of the T4 section.
The counter 6 counts the time Tx from the change to L. As a result, a digital signal corresponding to the input analog signal Ex can be obtained in the counter 6.

The above is the outline of the operation of the apparatus shown in FIG. 2. Next, the operation for increasing the resolution, which is a feature of the present invention, will be described.

The integral current I1 in the preliminary integration period T1 and the integral current I4 in the inverse integration period T4 have the relationship shown by the equation (7).

I1 = (1/4) × I4 (7) Therefore, one clock in the preliminary integration period is 1/4 of the inverse integration period T4.
Corresponds to the clock.

In FIG. 3, the timing indicated by the solid line is T1 = 1 clock, and the timing indicated by the broken line is T1 = 2 clock. Output of comparator 5 for the same input analog signal
The eB change timing is shifted by 1/4 clock.

In the present invention, the pre-integration period T1 provided before the double integration operation is controlled for each A / D conversion according to a predetermined sequence so that the pre-integration period T1 is evenly varied within a range of, for example, 1 to 4 clocks. Therefore, the output eB of the comparator 5 is evenly distributed at the time points from L to H in the range shown in the variation section of FIG. 4 (b).

Therefore, the count value (AD conversion value) of the counter 6 that counts the clock shown in (c) appears 1/4 when it is counted as K, and 3/4 when it is counted as (K-1). .

The arithmetic processing means 7 in the microprocessor 9 obtains a highly accurate AD conversion value Dx by averaging the count values of the counter 6.

That is, according to this example, the average calculation represented by the equation (8) is performed.

Dx = (1/4) x K + (3/4) x (K-1) = K- (3/4) ... (8) By performing such average calculation processing, the resolution of AD conversion can be increased. It can be improved four times.

Also, in order to obtain 4 times the resolution, at least 4 times
Although AD conversion is necessary, the amount of information up to the basic resolution can be obtained with one AD conversion. Therefore, as compared with the conventional one that achieves high resolution simply by increasing the integration time,
AD conversion time can be shortened.

Next, the entire flow of the basic A / D conversion operation in the device of the present invention will be described again with reference to FIGS. 3 and 4.

FIG. 3 shows one A / D conversion sequence (A / D conversion operation). Actually, this A / D conversion operation is performed by the integrator 1.
Is reset (the capacitor C is short-circuited by turning on the switch So) and is repeated as an initial state.

In this one A / D conversion operation, the integrator 1 uses the preliminary signal (Eb)
And a pre-integration operation of integrating the input analog signal (Ex) and the reference signal (Es).

That is, the control means 8 first controls the switch circuit 4, turns on the switch S3, applies the preliminary signal (Eb) to the integrator 1, and integrates it. The operation of integrating the preliminary signal (Eb) by the integrator 1 is called a preliminary integration operation.

Here, the time during which the preliminary integration operation is performed (preliminary integration operation time) T1 is from 1 pulse of the counting pulse given to the counting means (counter) 6 to N pulses (1 / N is an integrated current during the preliminary integration operation). The ratio of I1 and the integrated current I4 at the time of the reverse integration operation in which the reference signal is integrated in the double integration operation is I1 / I4 = 1/4 in the example of the formula (7) described above. Therefore, in this case, an arbitrary time is selected within the time of N = 4).

In FIGS. 3 (a), (d), (f), and (g), the characteristic indicated by the solid line is when the time T1 of this inverse integration operation is one pulse.

Then, the time T1 of the pre-integration operation is from one pulse of the counting pulse to N when the A / D conversion operation is repeated next.
Another time (for example, 2 to 4 pulses) will be selected within the time of the pulse.

Next, the control means 8 controls the switch circuit 4 to turn on the switch S1 and integrate the reference signal (+ Es) for a fixed time T2. It should be noted that this integration operation is selected when the input analog signal (Ex) takes a negative value as described above, and may be omitted.

Next, switch S4 is turned on, and the input analog signal (E
x) is applied to the integrator 1 for a fixed time T3 to perform input integration. After input integration is performed for a fixed time T3, switch S2 is turned on, and this time the reference signal (-Es)
Is applied to the integrator 1 to perform the inverse integration operation (integrated current I4).

Here, the above-described input integration operation and inverse integration operation are collectively referred to as a double integration operation, and this operation is similar to the conventional one.

When the inverse integration operation is performed, the output signal eA of the integrator 1 is, as shown in FIG. 3 (f), at the time of entering the section of T4 (the level of the signal eA at this time is the same as that of the input analog signal). Corresponding to the size) gradually changes toward the common level, and eventually reaches the common level.

The comparator 5 detects that the level of the signal eA from the integrator 1 has reached the common level, and stops the counting operation of the counter 6. As a result, the counter 6 counts counting pulses from the time the inverse integration operation is performed until the level of the signal eA reaches the common level (Tx).

As described above, by the preliminary integration operation and the double integration operation,
One A / D conversion operation (sequence) is completed, and the count value obtained by the counter 6 at this time becomes K, for example.
Here, the count value (A / D conversion value) K corresponds to the level of the signal eA of the integrator 1 immediately before starting the inverse integration operation,
It corresponds to the magnitude of the input analog signal.

However, the resolution is the basic resolution determined by the time allotted to count the pulses and the frequency of the counting pulses.

Then, the operation proceeds to the next A / D conversion operation (sequence), and similarly to the above, first the preliminary integration operation and then the double integration operation are performed, and similarly the count value corresponding to the input analog signal from the counter 6 is obtained. Is repeated. At this time
In the A / D conversion operation, the time T1 of the pre-integration operation is selected at different times within the time from 1 pulse to N pulses of the counting pulse.

In FIGS. 3 (a), (d), (f), and (g), the characteristic indicated by the broken line is when the time T1 of this preliminary integration operation is two counting pulses.

In this case, since the time during which the preliminary signal Eb is integrated is longer than that shown by the solid line, the level of the signal eA from the integrator 1 at the time of entering the section of T4 becomes the level shown by the solid line. In comparison, as indicated by the broken line, the absolute value is a slightly smaller value, and the counting section Tx is slightly shorter than that in the case of the solid line.

As a result, the count value of the counter 6 may be K-1 with respect to the count value K in the case of the solid line, depending on the degree to which the counting section is shortened.

Similarly, in the next A / D conversion operation,
The time T1 of the pre-integration operation is changed from 1 pulse of the counting pulse to N
A / D conversion operation is repeated by selecting different times within the pulse time.

Thus, assuming that the value of the input analog signal Ex is constant in a certain time range, each A / D performed in that time range is
Pre-integration operation time T1 for each conversion operation (sequence)
To change the initial value of the input integration operation (the integrator output at the time of entering the section T3) little by little within the range of 1 pulse to N pulses of the counting pulse so as to have different times. Therefore, the count value of the counter 6 can be intentionally varied even though the value of the input analog signal Ex is constant.

The arithmetic processing means 7 counts the counter value (for example, K, K−) obtained by the counter 6 by repeatedly performing each A / D conversion operation.
The averaging operation of 1) is performed a plurality of times (for example, 4 times), and a digital signal corresponding to the input analog signal can be obtained as shown in Expression (8).

The result of such an average calculation process has the same form as that in which the pulse interval of the counting pulse is interpolated, and the resolution of the A / D conversion can be improved more than the basic resolution described above.

The above description is based on the assumption that the pre-integration period T1 provided before the double-integration operation is evenly distributed within the range of, for example, 1 to 4 clocks. It is not easy to make them evenly distributed. It may be possible to use a random number signal, but in this case, although it is equalized when viewed over a long period of time, deviation occurs during a short period of time.

In the present invention, the pre-integration period T1 is changed in accordance with the sequence ai that satisfies the following requirements, within the range from 1 pulse to N pulses of the counting pulse in the counting means, so as to be uniformly varied. There is.

, Ai consists of n elements consisting of numerical values of 1, 2, 3, ... I ..., N, and is repeated as a1, a2, ... An, a1, a2 ,.

, The sequence ai is large with respect to its central value (n + 1) / 2,
They are arranged so that they are small, large, small, large, small ...

FIG. 5 is a diagram showing an example of a sequence ai satisfying the above-mentioned requirements, where n = 16. here
ai = {15,2,11,6,13,4,10,7,16,1,12,5,14,3,9,8}.

By changing the preliminary integration period T1 for each A / D conversion in the range from 1 pulse to N pulses of the counting pulse in the counting means in accordance with such a sequence of numbers, the preliminary integration period T1 is evenly varied. Therefore, a highly accurate A / D conversion value can be obtained.

FIG. 6 is a diagram showing an A / D conversion result according to the present invention, and FIG. 7 is a diagram showing an A / D conversion result when a random number signal is used in place of the sequence ai used in the present invention. Is.

Here, the preliminary integration period T1 is changed within the range of 1 pulse to 16 pulses of the counting pulse in the counting means, and the moving average result of 16 data is used as the A / D conversion data Dx as the average calculation. .

The present invention using the sequence ai, some deviation occurs until 16 data after the start, but the A / D conversion data after that is stable at a value close to the true value Ds, Satisfactory results have been obtained.

On the other hand, in the case of using the random number signal, the swell occurs around the true value Ds, and a good result is not obtained.

(Effect of the Invention) As described in detail above, according to the present invention, in the A / D conversion operation of the conventionally well-known double integration method, the auxiliary signal for integrating the auxiliary signal in the stage before the double integration operation is used. Integration operation period
T1 is provided and the time of this preliminary integration operation is
Every D conversion operation (sequence) is changed by a sequence signal having a predetermined requirement.
Intentionally and evenly, the A / D conversion value varies, and A
By performing an average calculation process of a plurality of A / D conversion values obtained in the / D conversion operation, the resolution of A / D conversion can be improved more than the basic resolution.

Further, the present invention is to increase the frequency of the counting pulse, A /
This is effective in that the resolution of A / D conversion can be easily improved without performing any special configuration or treatment such as lengthening the D conversion time.

[Brief description of drawings]

FIG. 1 is a basic block diagram of the present invention, and FIG. 2 is a block diagram showing an embodiment of the present invention, FIGS. 3 and 4.
FIG. 5 is a waveform diagram for explaining the operation, FIG. 5 is a diagram showing an example of a sequence signal used in the present invention, FIG. 6 is a diagram showing an A / D conversion result according to the present invention, and FIG. FIG. 8 is a diagram showing an A / D conversion result when a random number signal is used instead of a sequence signal according to the invention, FIG. 8 is a block diagram of a configuration of a conventional device, and FIGS. 9 and 10 are operation waveform diagrams thereof. 1 ... Integrator 2 ... Reference power supply 3 ... Preliminary integration power supply 4 ... Switch circuit 5 ... Comparator 6 ... Counting means 7 ... Arithmetic processing means 8 ... Control means 9 ... Microprocessor

Claims (1)

[Claims] 1. An integrator, a reference power supply, a preliminary integration power supply for outputting a preliminary signal having a value of a predetermined ratio to the value of a reference signal output from the reference power supply, an input analog signal (Ex), Reference signal (± Es) obtained from the reference power supply, backup signal (Eb) obtained from the backup integration power supply
A switch circuit for selecting and inputting to the integrator, a comparator for comparing the output of the integrator with the common potential, a counting means for counting the pulses based on the signal from the comparator, and a counting means An arithmetic processing means for inputting a count value and performing a predetermined average arithmetic processing, and a control means for inputting a signal from a comparator and controlling the switch circuit, the integrator, and the counting means, respectively, the control means are provided. , The switch circuit is controlled, first, the preliminary signal (Eb) is selected, and the preliminary signal is applied to the counting means from 1 pulse to N pulses (1 / N is a preliminary integration in which the preliminary signal is integrated. The ratio of the integrated current I1 during operation and the integrated current I4 during the inverse integration operation that integrates the reference signal) is applied to the integrator for an arbitrary time (T1) to perform preliminary integration operation, Next, input analog signal (Ex) And the reference signal (± Es) are sequentially selected and applied to the integrator to perform the double integration operation. Thereafter, the AD conversion operation including the preliminary integration operation and the double integration operation is performed at the time (T1 ) Is repeated according to the number sequence ai that satisfies the following requirements within the time from 1 pulse to N pulses of the counting pulse, and the arithmetic processing means obtains the counting means by the AD conversion operation performed repeatedly. A D / A converter characterized in that a digital signal corresponding to the input analog signal is obtained by averaging a plurality of calculated count values a plurality of times. Note that the sequence ai consists of n elements consisting of numerical values of 1,2,3, ... i ..., n, and is repeated as a1, a2, ... an, a1, a2 ,. , The sequence ai is large with respect to its central value (n + 1) / 2,
They are arranged so that they are small, large, small, large, small ...