JPS61230521A - Calibration method of integration and converter and integration ad converter using said calibration method - Google Patents

Calibration method of integration and converter and integration ad converter using said calibration method

Info

Publication number
JPS61230521A
JPS61230521A JP7208085A JP7208085A JPS61230521A JP S61230521 A JPS61230521 A JP S61230521A JP 7208085 A JP7208085 A JP 7208085A JP 7208085 A JP7208085 A JP 7208085A JP S61230521 A JPS61230521 A JP S61230521A
Authority
JP
Japan
Prior art keywords
reference current
value
current source
time
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7208085A
Other languages
Japanese (ja)
Other versions
JPH0253975B2 (en
Inventor
Hidekazu Yada
矢田 英一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to JP7208085A priority Critical patent/JPS61230521A/en
Publication of JPS61230521A publication Critical patent/JPS61230521A/en
Publication of JPH0253975B2 publication Critical patent/JPH0253975B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To eliminate an error generated due to response delay in a voltage comparator and to apply correct AD conversion at all times by providing a current correction means to the 2nd and 3rd reference current source, giving a correction data to them for calibration. CONSTITUTION:The 2nd reference current source 2 and the 3rd reference current source 3 are provided with DA converters 17, 18 constituting the current correction means, correction currents i4, i5 are given by giving a correction data respectively to the DA converters 17, 18 and the current i4, i5 are set so as to satisfy the relation of current ratio i1/(i1+i4)= specified value A and (i2+i4)/(i3+i5)= specified value B with respect to the actual current ratios i1/i2 and i2/i3. Then an error generated due to the response delay of a voltage comparator 11 is eliminated by applying the calibration in this way at the start of use and the correct calibration is applied automatically so as to apply correct AD conversion at all times.

Description

【発明の詳細な説明】 「産業上の利用分野」 この発明は例えば電圧電流測定等C;利用されている積
分形AD変換器の改良≦二関する。
DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to, for example, voltage and current measurements, etc.; improvements in integral type AD converters used;

「従来技術」 積分形AD変換器は被測定信号(電圧信号電流信号)を
一定時間第1積分し、この積分電圧がゼロに戻る方向に
基準電流源から被測定信号と逆極性の基準電流を与え第
2積分を行なう。この第2積分を行なっている時間を概
知の同波数を持つクロックパルスをカウンタL:よって
計測し、この計測値を被測定信号のディジタル値として
得るAD変換方°式である。
"Prior art" An integral type AD converter first integrates the signal under test (voltage signal/current signal) for a certain period of time, and then supplies a reference current with the opposite polarity to the signal under test from a reference current source in the direction in which the integrated voltage returns to zero. Then, perform the second integral. This is an AD conversion method in which a clock pulse having the same known wave number is measured by a counter L during the second integration, and this measured value is obtained as a digital value of the signal under test.

AD変換の精度を向上させる目的で第2積分の終了後C
ユ第3積分及び第4積分を行なうマルチスロープ形のA
D変換器が実用されている。
C after the completion of the second integration for the purpose of improving the accuracy of AD conversion.
Multi-slope type A that performs the third and fourth integrals
D converters are in practical use.

第3図乃至第5図を用いて従来のマルチスロープ形AD
変換器の構造及び動作C:ついて説明する。
Conventional multi-slope type AD using Figures 3 to 5
The structure and operation of the converter C: will be explained.

この例では三つの基準電流[1,2,3を有し、これら
基準電流源1.2 t 3 cよって被測定電圧vxを
一定時間第1積分した後C;、第2、第3、第4積分ま
で行なうよう(ユしたマルチスロープ形AD変換器の場
合を示す。
In this example, there are three reference currents [1, 2, and 3. The case of a multi-slope AD converter that performs up to 4 integrations is shown.

図中4はアナログ積分器を示す。このアナログ積分器4
の入力側C切替回路5が設けられる。切替回路5は被測
定電圧vxを抵抗器13を通じて電流信号ixに変換し
てアナログ積分器4c二与える状態と、第1基準電流源
1の基準電流11をアナログ積分器4 C与える状態と
、第2基準電流源2の基準電流igyz’アナログ積分
器4に与える状態と、第3基準電流源3の基準電流js
t’アナログ積分器4(−与える状態(;切替る動作を
行なう。
In the figure, 4 indicates an analog integrator. This analog integrator 4
An input side C switching circuit 5 is provided. The switching circuit 5 converts the voltage to be measured vx into a current signal ix through the resistor 13 and supplies it to the analog integrator 4c, a state where the reference current 11 of the first reference current source 1 is supplied to the analog integrator 4c, and a state where the current signal ix is supplied to the analog integrator 4c. The state of the reference current igyz' of the second reference current source 2 and the state given to the analog integrator 4, and the reference current js of the third reference current source 3
t' Analog integrator 4 (-giving state (; performs switching operation.

切替回路5の具体的な構造としては一般(−電界効果ト
ランジスタを用いたアナログスイッチ素子sw、、sW
2.sw3.sw4が用いられる。これらのスイッチ素
子SW1〜SW4はスイッチ駆動回路5ACよってオン
オフ駆動される。スイッチ駆動回路5Aは例えばマイク
ロコンピュータ(:よって構成される制御器6の指令(
:よって制御される。
The specific structure of the switching circuit 5 is general (-analog switch elements sw, sW using field effect transistors).
2. sw3. sw4 is used. These switch elements SW1 to SW4 are turned on and off by a switch drive circuit 5AC. The switch drive circuit 5A receives commands from a controller 6 configured by, for example, a microcomputer (
: Controlled accordingly.

7はこの制御器6を所定の順序で動作させるためのプロ
グラムを収納したROMY示す。8は毎回のAD変換値
等を一時記憶するRAMを示す。9はクロックパルス源
を示す。
Reference numeral 7 indicates a ROMY that stores a program for operating the controller 6 in a predetermined order. Reference numeral 8 indicates a RAM that temporarily stores AD conversion values and the like each time. 9 indicates a clock pulse source.

アナログ積分器4の出力側C二は電圧比較器11を設け
、この電圧比較器11によってアナログ積分器4の積分
電圧Vがゼロ点を通過する状態を検出Tる動作を行なわ
せている。12はクロックパルス源9のクロックパルス
Pcを計数し、AD変換値を得るためのカウンタを示す
A voltage comparator 11 is provided on the output side C2 of the analog integrator 4, and the voltage comparator 11 performs an operation of detecting the state in which the integrated voltage V of the analog integrator 4 passes through the zero point. Reference numeral 12 indicates a counter for counting the clock pulses Pc of the clock pulse source 9 and obtaining an AD conversion value.

(動 作) この回路構造において切替回路5は先ず被測定電圧vx
を選択し、抵抗器13を通じてアナログ積分器4゛C:
被測定電圧源vxから電流IXを与え、この電流ixを
第4図(;示すよう(−一定時間T1だけ積分する。こ
の積分状態を第1積分期間M0と称す。第1積分終了後
に切替回路5はスイッチ素子SWlをオフにし、スイッ
チ素子SW2をオンに制御して被測定電圧vxとは逆極
性の電圧−vlを抵抗器14を通じて与え、第1基準電
流11をアナログ積分器4に与え、第2積分期間M2に
入る。第2積分期間M2が開始されるとカウンタ12は
クロックパルス源9から与えられるクロックパルスPC
の計数を始める。アナログ積分器4の積分電圧Vがゼロ
点を通過すると電圧比較器11がこれを検出し、この検
出直後の1個目のクロックパルスPc1(第4図)C:
同期して第2積分動作を停止させる。このためCユアナ
ログ積分器4の積分電圧Vは第4図(−示すよう(;ゼ
ロ点かられずかな量だけ逆極性の電圧C:行過ぎる。
(Operation) In this circuit structure, the switching circuit 5 first changes the voltage to be measured vx
Select analog integrator 4゛C through resistor 13:
A current IX is applied from the voltage source to be measured vx, and this current ix is integrated for a fixed time T1 as shown in FIG. 5 turns off the switch element SWl, controls the switch element SW2 to turn on, applies a voltage -vl of opposite polarity to the voltage to be measured vx through the resistor 14, and applies the first reference current 11 to the analog integrator 4; The second integration period M2 begins. When the second integration period M2 starts, the counter 12 receives the clock pulse PC from the clock pulse source 9.
Start counting. When the integrated voltage V of the analog integrator 4 passes through the zero point, the voltage comparator 11 detects this, and immediately after this detection, the first clock pulse Pc1 (FIG. 4) C:
The second integral operation is stopped in synchronization. Therefore, the integrated voltage V of the C analog integrator 4 exceeds the voltage C of opposite polarity by a small amount from the zero point, as shown in FIG.

この状態で切替回路5はスイッチ素子SW2をオフに戻
し、スイッチ素子S Wsをオン鴫こする。この切替動
作によってアナログ積分器4には第2基準電流源2から
第1基準電流11とは逆極性の基準電流12が与えられ
第3積分期間M81m入る。第3積分期間M8ではアナ
ログ積分器4の積分電圧は再び逆向の方向C二向って変
化する。積分電圧Vがゼロ点を横切ると次のクロックパ
ルスPc2C同期して第3積分を終了する。第3積分が
終了すると切替回路5はスイッチ素子S WsをオフC
;し、スイッチ素子5W4Vオンに制御する。この切替
(−よってアナログ積分器4に第3基準電流源3から第
3基準電流i3が与えられる。第3基準電流i3が与え
られることによってアナログ積分器4の積分電圧はゼロ
点に向って変化し、ゼロクロス点で第4積分ヲ終了する
In this state, the switching circuit 5 turns off the switch element SW2 and turns on the switch element SWs. By this switching operation, the analog integrator 4 is supplied with a reference current 12 having a polarity opposite to that of the first reference current 11 from the second reference current source 2, and a third integration period M81m is entered. In the third integration period M8, the integrated voltage of the analog integrator 4 changes again in the opposite direction C. When the integrated voltage V crosses the zero point, the third integration is completed in synchronization with the next clock pulse Pc2C. When the third integration is completed, the switching circuit 5 turns off the switch element SWs.
;Then, the switch element 5W4V is controlled to be on. This switching (-Therefore, the third reference current i3 is given to the analog integrator 4 from the third reference current source 3. By providing the third reference current i3, the integrated voltage of the analog integrator 4 changes toward the zero point. Then, the fourth integral ends at the zero cross point.

第1基準電流itと第2基準電流12及び第3基準電流
i3の比をそれぞれ例えば1:1/10:1/1D、の
よう(:設定し、第2積分期間M2ではカウンタ12の
上位ビットの入力端子C:クロックパルスPCを入力し
て計数させ、第3積分期間M8ではカウンタの中位桁の
入力端子(−クロックパルスPcを与え、第3積分期間
M4では更に下位桁ビットの入力端子にクロッ“クパル
スPcを与えて計数させることC;より被測定電圧vx
の値を下位の桁まで分解能よ<AD変換することができ
る。
The ratio of the first reference current it, the second reference current 12, and the third reference current i3 is set as, for example, 1:1/10:1/1D, respectively, and in the second integration period M2, the upper bit of the counter 12 is Input terminal C: inputs the clock pulse PC to count, and in the third integration period M8, the input terminal of the middle digit of the counter (- gives the clock pulse Pc, and in the third integration period M4, the input terminal of the lower digit bit) Applying a clock pulse Pc to make it count; the voltage to be measured vx
It is possible to convert the value of <A/D with resolution down to the lower digits.

「発明が解決しようとする問題点」 第3図に示した従来のマルチスロープ形AD変換器C;
おいて、第1、第2、第3基準電流源1゜2.3の各電
流値が例えば1:1/10:1/1D、のように正確(
;その比率が設定されていれば第1、第2、第3積分期
間M2 p MS + M4で得られるディジタル値は
直線性C;優れた精度の高いAD変換値を得ることがで
きる。
"Problems to be Solved by the Invention" Conventional multi-slope AD converter C shown in FIG.
In this case, each current value of the first, second, and third reference current sources 1°2.3 is accurate (for example, 1:1/10:1/1D).
; If the ratio is set, the digital values obtained in the first, second, and third integration periods M2 p MS + M4 have linearity C; it is possible to obtain an AD conversion value with excellent accuracy.

ところで第1基準電流源1、第2基準電流源2、第3基
準電流源3の電流比が初期の値からずれたとすると第2
積分期間M2で得られるディジタル値と第2積分期間M
8で得られるディジタル値及ヒ第3積分期間M4で得ら
れるディジタル値C二は相互(;誤差を含むものとなり
精度が悪くなる不都合が生じる。
By the way, if the current ratio of the first reference current source 1, the second reference current source 2, and the third reference current source 3 deviates from the initial value, the second
Digital value obtained in integration period M2 and second integration period M
The digital value C2 obtained in step 8 and the digital value C2 obtained in the third integration period M4 contain mutual errors, resulting in a problem of poor accuracy.

第1基準電流源1と、第2基準電流源2及び第3基準電
流源3の各電流il、 i、・18の値tそれぞれ直接
測定することができればその比を求めて初期の値C;修
正することができる。然し乍ら通常の利用者が基準電流
源1,2.3の各電流値を直接測定し、その比が初期の
設定値(ニ一致しているか否かを判定し、一致していな
いときは基準電流源の各電流値i1. i2. i3を
修正する如き作業を行なうことは困難なことである。
If the values t of the currents il, i, .multidot.18 of the first reference current source 1, second reference current source 2, and third reference current source 3 can be directly measured, calculate the ratio and initial value C; Can be fixed. However, a normal user can directly measure each current value of the reference current sources 1, 2.3, and determine whether the ratio matches the initial setting value (d), and if they do not match, the reference current It is difficult to perform operations such as modifying each current value i1, i2, i3 of the source.

このため本出願人は第、1基準電流源1の第1基準電流
11を一定時間第l積分し、この第1積分の結果得られ
たアナログ積分器4の積分電圧がゼロ(;戻るまで第2
基準電流源2の基準電流12ン第2積分し、第1積分時
間と第2積分時間の比から基準電流11と12の比を求
めその比の値を利用してAD変換値を補正するよう(−
構成した積分゛形AD変換器を提案している。
For this reason, the present applicant integrates the first reference current 11 of the first reference current source 1 for a certain period of time until the integrated voltage of the analog integrator 4 obtained as a result of this first integration returns to zero (; 2
A second integration is performed on the reference current 12 of the reference current source 2, and the ratio of the reference currents 11 and 12 is calculated from the ratio of the first integration time and the second integration time, and the AD conversion value is corrected using the value of the ratio. (−
We are proposing an integral type AD converter.

この方式を採る積分形AD変換器によれば基準電流源の
電流比が初期の状態からずれたとしても自動的に補正が
行なわれ常じ正しいAD変換を行なうことができる。
According to an integral type AD converter adopting this method, even if the current ratio of the reference current source deviates from its initial state, correction is automatically performed and correct AD conversion can always be performed.

然し乍らこの方式には次のような不都合が存在する。゛ つまり第1基準電流源lの基準電流11を第1積分し、
第2基準電流源2の基準電流j2Y第2積分した場合、
その電流比を第1積分時間と第2積分時間の比によって
求めるため番−は第2積分時間の終了はアナログ積分器
4の積分電圧Vがゼロ(ユ戻った時点CLなければなら
ない。このため校正モードでは第5図(−示すように第
2積分期間M2の終了はアナログ積分器4の積分電圧が
ゼロに戻った時点を・検出し、第1積分時間Taと第2
積分時間Ti)の比TV−(:よって第1基準電流11
と第2基準電流量2の比i、/i2を求めて・いる。つ
まり電荷の平衡条件が1tTa  i2’rb=oであ
るからii/i 2 ” Ttly/1′;1となり、
時間TaとTb¥カウンタ12の計数値C;よって知る
ことC;よりil/i2を測定することができる。
However, this method has the following disadvantages. In other words, the reference current 11 of the first reference current source l is first integrated,
When the reference current j2Y of the second reference current source 2 is second integrated,
In order to find the current ratio by the ratio of the first integration time and the second integration time, the end of the second integration time must be the point CL when the integrated voltage V of the analog integrator 4 returns to zero (Y). In the calibration mode, as shown in FIG.
The ratio TV-(: Therefore, the first reference current 11
and the second reference current amount 2, the ratio i, /i2 is calculated. In other words, since the charge equilibrium condition is 1tTa i2'rb=o, ii/i 2 ''Ttly/1';1,
il/i2 can be measured from the time Ta and the count value C of the Tb\ counter 12; therefore, knowing C;.

然し乍らアナログ積分器4の積分電圧がゼロC:戻った
ことを検出する電圧比較器11は応答速度が比較的遅い
ため、その遅れ時間が誤差として含まれる不都合が生じ
る。つまり電圧比較器11の応答遅れ時間をT。とする
と第2積分時間は第5図C二本す1うCTb+ T(と
なり、時間Tcが誤差となる。
However, since the voltage comparator 11 that detects that the integrated voltage of the analog integrator 4 has returned to zero C has a relatively slow response speed, there is a problem that the delay time is included as an error. In other words, the response delay time of the voltage comparator 11 is T. Then, the second integral time becomes CTb+T(2 lines C in FIG. 5), and the time Tc becomes an error.

この発明の目的は電圧比較器11の遅れ時間TcC:よ
る誤差を除去することができ、然も自動的C二修正を行
なうことができる積分形AD変換方式と積分形AD変換
器を提供しようとするものである。
An object of the present invention is to provide an integral type AD conversion method and an integral type AD converter that can eliminate errors caused by the delay time Tc of the voltage comparator 11 and also can automatically correct C2. It is something to do.

[問題点を解決するための手段」 この発明では第1基準電流源の電流を異なる時間で少な
くとも二回積分し、それぞれの第1積分に対して第2基
準電流源の電流(:よって第2積分を二回行ない、二回
の第2積分(−よって得られた時間値の差を求めること
(;よって電圧比較器の遅れ時間Tcを除去した時間値
を得るようCL、この差の時間値と第1積分時間から第
1基準電流と第2基準電流の真の比を求める校正方法を
提案し、更(−この校正方法を用いた積分形AD変換器
を提供するものである。
[Means for Solving the Problems] In the present invention, the current of the first reference current source is integrated at least twice at different times, and the current of the second reference current source (: therefore, the second Perform the integration twice, and calculate the difference between the obtained time values by performing the second integration twice (; Therefore, calculate the time value CL to obtain the time value with the delay time Tc of the voltage comparator removed, and calculate the time value of this difference. The present invention proposes a calibration method for determining the true ratio of the first reference current and the second reference current from the first integration time, and further provides an integral type AD converter using this calibration method.

この発明(−よれば電圧比較器の応答遅れ(:伴なって
発生する誤差を除去した正確な電流比を求めること”が
でき、精度が高い校正を行なうことができる。
According to this invention, it is possible to obtain an accurate current ratio that eliminates the response delay of the voltage comparator and the error that occurs, and highly accurate calibration can be performed.

「実施例」 第1図を用いてこの出願の第1発明である校正方法C二
ついて説明する。この発明シーよる積分形AD変換器の
校正方法は第1基準電流源1の第1基準電流i1cよっ
て第1図じ示すようC二互に時間を異ならせて二回第1
積分を行なう。図中v1は一回目α秦キ積分動作時のア
ナログ積分器11の積分電圧波形、v2は二回目のアナ
ログ積分器11の積分電圧波形を示す。この例ではTa
□= 2 Ta□とした場合な示す。
"Example" Two calibration methods C, which are the first invention of this application, will be explained using FIG. The method for calibrating an integral type AD converter according to this invention is to calibrate the first reference current i1c of the first reference current source 1 twice at different times as shown in Figure 1.
Perform the integration. In the figure, v1 shows the integrated voltage waveform of the analog integrator 11 during the first α-Q integration operation, and v2 shows the integrated voltage waveform of the analog integrator 11 during the second time. In this example, Ta
The case where □=2 Ta□ is shown.

一回目の校正用第1積分C対して第2基準電流源2 C
よって校正用の第2積分を行なう。−回目の第1積分時
間ンT’at、第2積分時間ンTbx+Tctとする。
The second reference current source 2 C for the first integral C for the first calibration.
Therefore, a second integration for calibration is performed. -th first integration time T'at and second integration time Tbx+Tct.

二回目の第1積分!一対して第2基準電流源2砿:よっ
て第2積分を行なう。この第1積分時間なTal!、第
2積分時間をTbg +Tcgとする。
Second first integral! On the other hand, the second reference current source 2: Therefore, the second integration is performed. This first integral time Tal! , the second integration time is Tbg +Tcg.

二回の校正用AD変換動作により一回目の第2積分時間
(Tbt ” Tct )と、二回目の第2積分時間(
Tbg + Tc2)が得られる。TCt ”F Tc
gとすれば(Tbz +Tcs )  (Tb1+Tc
t )となる。ここで第1積分時間の関係を2 T31
 = Tagとしたから第2積分時間の関係も2 Tb
t = Tb2となる。
By performing two calibration AD conversion operations, the second integration time (Tbt ” Tct ) of the first time and the second integration time (Tct ” Tct ) of the second time are
Tbg + Tc2) is obtained. TCt”F Tc
If g, (Tbz +Tcs) (Tb1+Tc
t). Here, the relationship between the first integration time is 2 T31
= Tag, so the relationship between the second integration time is also 2 Tb
t=Tb2.

よって (Tbg +’ro1)   (Tbt +TC1)=
Tbt・・・・・・・・・・・・(1) となる。第1式で得られた時間値Tbtは電圧比較器1
1の遅れ時間Tcを含まない値である。
Therefore, (Tbg +'ro1) (Tbt +TC1)=
Tbt・・・・・・・・・(1) The time value Tbt obtained from the first equation is the voltage comparator 1
This value does not include the delay time Tc of 1.

電荷平衡の関係から ’I T’ai + ’2・TI)1     ・・・
・・・・・・・・・(2)であるからこの第2式から ==兜      ・・・・・・・・・・・・(3)I
2T’at が得られる。第3式(−おいて第1積分時間Ta□は予
め決めた一定時間であるから機知の値であり、二回のA
D変換動作によって得られたAD変換値(Tbi + 
Tc1)と(Tbg + TC?)によってTb1を第
1式から求めることによって電流比11/’2 ’に求
メることができる。
From the relationship of charge balance, 'IT'ai + '2・TI)1...
・・・・・・・・・・・・(2) Therefore, from this second equation == Kabuto ・・・・・・・・・・・・(3) I
2T'at is obtained. In the third equation (-, the first integral time Ta□ is a predetermined constant time, so it is a wise value, and the two
AD conversion value (Tbi +
By determining Tb1 from the first equation using Tc1) and (Tbg + TC?), the current ratio 11/'2' can be determined.

電流°比i 、/i 、を予めA(Aは例えば10.1
D、のような値≦;選定する)と規定しておくことC二
より二回の校正用AD変換動作により電流比jl/j2
の規定値Aからのずれを求めることができる。よってこ
の電流比i 1/l 2が予め規定した値Aとなるよう
C;例えば第2基準電流源2の電流12を修正すること
によって正しいAD変換動作を行なうことができる状態
に補正することができる。
The current ratio i, /i is set in advance to A (A is, for example, 10.1
(Select a value such as D ≦;).
The deviation from the specified value A can be determined. Therefore, it is possible to correct the current ratio i1/l2 to a predetermined value A; for example, by correcting the current 12 of the second reference current source 2, it is possible to perform a correct AD conversion operation. can.

第2基準電流源2と第3基準電流源3の間の関係も同様
(−シて電流比i2/isを求めることができる。この
電流比i2/i3を予めBと規定しておくことC;よっ
て二回のAD変換動作から実際の電流比127r、zr
:求め、その結果から規定値Bからのずれを求めること
ができる。
Similarly, the relationship between the second reference current source 2 and the third reference current source 3 can be determined by calculating the current ratio i2/is. This current ratio i2/i3 is defined as B in advance. ; Therefore, the actual current ratio from two AD conversion operations is 127r, zr
: can be determined, and the deviation from the specified value B can be determined from the result.

よってこの発明C;よる校正方法C二よれば電圧比較器
11の応答遅れに伴なう誤差を含むことなく正確な電流
比i、/i2及びi2/i8を求めることができ、正し
い校正を行なうことができる。
Therefore, according to the calibration method C2 according to the present invention C, accurate current ratios i, /i2 and i2/i8 can be obtained without including errors due to response delay of the voltage comparator 11, and correct calibration can be performed. be able to.

′  「第2発明の実施例」 この出願の第2発明では第2図に示すように、例えば第
2基準電流源2と第3基準電流源31=電流補正手段を
構成するDA変換器17と18を設け、このDA変換器
17と18C:それぞれ修正データを与えること(:よ
って修正電流i4及びi5を与え、この修正電流i4及
びi5を与えることによって電流比”1/ (”2 +
 ’4)!=A及び(i11+”4)/(is+1s)
=Bが満されるよう≦:i4とi、を設定するよう3ユ
構成したものである。
``Embodiment of the second invention'' In the second invention of this application, as shown in FIG. 18 is provided, and correction data is provided to the DA converters 17 and 18C, respectively.
'4)! =A and (i11+”4)/(is+1s)
The three units are configured to set ≦:i4 and i so that =B is satisfied.

尚校正モード時に第1基準電流源1の電流11を互C;
異なる所定時間で二回積分し、その積分電圧がそれぞれ
ゼロに戻るまで第2基準電流源2の電流12を積分し、
この第2基準電流源2の基準電流12を積分している二
つの時間をカクンタ121;よって求め、この二つの時
間値の差を求める手段と、この差の時間値と第1基準電
流を積分している時間との比を求める手段と、 時間の比が予め規定した値と一致しているか否かを判定
し、不一致の場合規定値からのずれ量を求める手段はマ
イクロコンピュータから成る制御器6(:よって構成さ
れる。
In addition, in the calibration mode, the current 11 of the first reference current source 1 is changed to C;
Integrating the current 12 of the second reference current source 2 twice at different predetermined times, and integrating the current 12 of the second reference current source 2 until each integrated voltage returns to zero,
A means for determining the difference between these two time values, and integrating the time value of this difference and the first reference current. A controller consisting of a microcomputer is used to determine whether the time ratio matches a predetermined value and to determine the amount of deviation from the predetermined value if the time ratio does not match the predetermined value. 6 (: Therefore, it is constituted.

つま°り二回の校正用AD変換動作(ユよって実際の電
流比i1/i2及び12/’sを求め、この実際の電流
比ζ;よって規定値A及びBからのずれ量を求め、その
ずれを修正する値を制御器6(;よって算出し、その算
出した値’&DA変換器17及び18L;与え、そのD
A変換出力を抵抗器1,9及び20を通じて第2基準電
流源2及び第3基皐電流源3の電流12と18に加えて
校正する。
In other words, the AD conversion operation for calibration is performed twice (by determining the actual current ratios i1/i2 and 12/'s, and calculating the deviation from the specified values A and B by calculating the actual current ratio ζ). A value for correcting the deviation is calculated by the controller 6 (; and the calculated value '&DA converters 17 and 18L;
The A conversion output is added to the currents 12 and 18 of the second reference current source 2 and the third reference current source 3 through resistors 1, 9 and 20 for calibration.

このよう(−構成することによって例えば使用開始毎C
;校正モードで動作させ、この校正モード(−おいて校
正値をDA変換器17と18C与えて校正すること(:
より、常に正しいAD変換を行なうことができる。
Like this (- for example by configuring C
; Operate in calibration mode, and calibrate by applying calibration values to DA converters 17 and 18C in this calibration mode (-).
Therefore, correct AD conversion can always be performed.

「発明の効果」 上述したようC二この出願の第1発明(−よれば電圧比
較器11の応答遅れC二伴なって発生する誤差を除去し
た正しい校正を行なうことができる。
"Effects of the Invention" As described above, according to the first invention of this application (-), correct calibration can be performed by eliminating errors caused by the response delay of the voltage comparator 11.

またこの出願の第2発明C二よれば電圧比較器11の応
答遅れ(−よって発生する誤差を除去した正しい校正を
自動的に行なうことができる。よって常C:正しいAD
変換動作を行なうAD変換器を提供できる。
Further, according to the second invention C2 of this application, it is possible to automatically perform correct calibration that eliminates the error caused by the response delay (-) of the voltage comparator 11. Therefore, always C: Correct AD
An AD converter that performs a conversion operation can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの出願の第1発明の詳細な説明するための波
形図、第2図はこの出願の第2発明の詳細な説明するた
めのブロック図、第3図は従来技術を説明゛するための
ブロック図、第4図及び第5図は従来の積分形AD変換
器の動作を説明するための波形図である。 1:第1基準電流源、2:第2基準電流源、3:第3基
準電流源、4:アナログ積分器、5:切替回路、5A:
スイッチ駆動回路、6:制御器、7:ROM、8:RA
M、9:クロックパルス源、11:電圧比較器、12:
カクンタ、17 、18 :電流補正手段を構成するD
A変換器。 特許出願人  タケダ理研工業株式会社代  理  人
   草   野     卓il 口 オ 5回
FIG. 1 is a waveform diagram for explaining in detail the first invention of this application, FIG. 2 is a block diagram for explaining in detail the second invention of this application, and FIG. 3 is for explaining the prior art. FIGS. 4 and 5 are waveform diagrams for explaining the operation of a conventional integral type AD converter. 1: First reference current source, 2: Second reference current source, 3: Third reference current source, 4: Analog integrator, 5: Switching circuit, 5A:
Switch drive circuit, 6: Controller, 7: ROM, 8: RA
M, 9: Clock pulse source, 11: Voltage comparator, 12:
Kakunta, 17, 18: D constituting current correction means
A converter. Patent applicant: Takeda Riken Kogyo Co., Ltd. Representative: Takuil Kusano 5 times

Claims (2)

【特許請求の範囲】[Claims] (1)A、少なくとも第1基準電流源及びこの第1基準
電流源と極性を異にし電流値が第1基準電流源の電流値
より小さい値に設定された第2基準電流源を有し、これ
ら二つの基準電流源から出力される第1基準電流及び第
2基準電流によって被測定信号の積分値に対し第2積分
及び第3積分を行ない、第2積分時間値と第3積分時間
値によって被測定信号の量をディジタル値に変換する構
造の積分形AD変換器において、 B、校正モード時に上記第1基準電流源の電流を互に異
なる所定時間で二回積分し、その積分電圧がそれぞれゼ
ロに戻るまで上記第2基準電流源の電流を積分し、この
第2基準電流源の基準電流を積分している二つの時間を
求め、この二つの時間値の差の値から誤差を含まない真
のAD変換値を求め、この真のAD変換値と上記第1基
準電流を積分している時間との比から上記第1基準電流
値と第2基準電流値の比を求め、この電流値の比が所定
値となるように上記第1基準電流と第2基準電流の値を
修正し正しいAD変換を行なうことができるようにした
積分形AD変換器の校正方法。
(1) A, having at least a first reference current source and a second reference current source having a polarity different from that of the first reference current source and having a current value set to a value smaller than the current value of the first reference current source; The first and second reference currents output from these two reference current sources perform second and third integration on the integral value of the signal under test, and the second and third integral time values are used to In an integral type AD converter configured to convert the amount of the signal under measurement into a digital value, B. In the calibration mode, the current of the first reference current source is integrated twice at different predetermined times, and the integrated voltages are respectively Integrate the current of the second reference current source until it returns to zero, find the two times during which the reference current of this second reference current source is integrated, and calculate the difference between these two time values without including the error. Determine the true AD conversion value, calculate the ratio of the first reference current value and the second reference current value from the ratio of this true AD conversion value and the time during which the first reference current is integrated, and calculate this current value. A method for calibrating an integral type AD converter, in which correct AD conversion can be performed by correcting the values of the first reference current and the second reference current so that the ratio of the first reference current and the second reference current becomes a predetermined value.
(2)A、少なくとも第1基準電流源及びこの第1基準
電流源と極性を異にし電流値が第1基準電流源の電流値
より小さい値に設定された第2基準電流源を有し、これ
ら二つの基準電流源から出力される第1基準電流及び第
2基準電流によって被測定信号の積分値に対し第2積分
及び第3積分を行ない、第2積分時間値と第3積分時間
値によって被測定信号の量をディジタル値に変換する構
造の積分形AD変換器において、 B、校正モード時に上記第1基準電流源の電流を互に異
なる所定時間で二回積分し、その積分電圧がそれぞれゼ
ロに戻るまで上記第2基準電流源の電流を積分し、この
第2基準電流源の基準電流を積分している二つの時間を
求め、この二つの時間値の差を求める手段と、C、この
差の時間値と第1基準電流を積分している時間との比を
求める手段と、 D、時間の比が予め規定した値と一致しているか否かを
判定し、不一致の場合規定値からのずれ量を求める手段
と、 E、このずれ量から上記第2基準電流源の電流値を修正
し、上記時間の比が規定値となるように校正する電流補
正手段と、 を具備して成る積分形AD変換器。
(2) A, having at least a first reference current source and a second reference current source having a polarity different from that of the first reference current source and having a current value set to a value smaller than the current value of the first reference current source; The first and second reference currents output from these two reference current sources perform second and third integration on the integral value of the signal under test, and the second and third integral time values are used to In an integral type AD converter configured to convert the amount of the signal under measurement into a digital value, B. In the calibration mode, the current of the first reference current source is integrated twice at different predetermined times, and the integrated voltages are respectively means for integrating the current of the second reference current source until it returns to zero, determining two times during which the reference current of the second reference current source is integrated, and determining a difference between these two time values; means for determining the ratio between the time value of this difference and the time during which the first reference current is integrated; D. determining whether the time ratio matches a predetermined value; E. current correction means for correcting the current value of the second reference current source based on the deviation amount and calibrating the time ratio so that it becomes a specified value. An integral type AD converter consisting of:
JP7208085A 1985-04-05 1985-04-05 Calibration method of integration and converter and integration ad converter using said calibration method Granted JPS61230521A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7208085A JPS61230521A (en) 1985-04-05 1985-04-05 Calibration method of integration and converter and integration ad converter using said calibration method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7208085A JPS61230521A (en) 1985-04-05 1985-04-05 Calibration method of integration and converter and integration ad converter using said calibration method

Publications (2)

Publication Number Publication Date
JPS61230521A true JPS61230521A (en) 1986-10-14
JPH0253975B2 JPH0253975B2 (en) 1990-11-20

Family

ID=13479074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7208085A Granted JPS61230521A (en) 1985-04-05 1985-04-05 Calibration method of integration and converter and integration ad converter using said calibration method

Country Status (1)

Country Link
JP (1) JPS61230521A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01282927A (en) * 1988-05-09 1989-11-14 Yokogawa Electric Corp A/d converter
JP2009124392A (en) * 2007-11-14 2009-06-04 Tanita Corp Ad converter and scale

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01282927A (en) * 1988-05-09 1989-11-14 Yokogawa Electric Corp A/d converter
JP2009124392A (en) * 2007-11-14 2009-06-04 Tanita Corp Ad converter and scale

Also Published As

Publication number Publication date
JPH0253975B2 (en) 1990-11-20

Similar Documents

Publication Publication Date Title
US5101206A (en) Integrating analog to digital converter
US4357600A (en) Multislope converter and conversion technique
JPS5948571B2 (en) analog digital converter
JPS6219094B2 (en)
JPS5815982B2 (en) Analog ↓-digital conversion circuit
US4568913A (en) High speed integrating analog-to-digital converter
JPS61230521A (en) Calibration method of integration and converter and integration ad converter using said calibration method
JP2776598B2 (en) Analog-to-digital converter
JPS6255735B2 (en)
JPS6141918A (en) Error correcting device for flying capacitor multiplexer circuit
JPH057781Y2 (en)
JPS636889Y2 (en)
JPS5948572B2 (en) analog digital converter
JPH0772187A (en) Voltage measuring instrument
JPH01227525A (en) D/a converter
JPH0758911B2 (en) Integral A / D converter
SU1251327A1 (en) Method and apparatus for analog-to-digital conversion
SU1654657A1 (en) Device for measurement errors correction
SU789767A1 (en) Digital measuring in balanced bridge
SU1234730A1 (en) Multichannel digital thermometer
JPH0786948A (en) Analog/digital converter
JP3629327B2 (en) Double integration type A / D conversion method and circuit, and double integration arithmetic circuit
JPH055514Y2 (en)
JPH065226U (en) Analog / digital converter
JPH0331205B2 (en)

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term