JPH01282927A - A/d converter - Google Patents

Abstract

PURPOSE:To obtain a digital signal with simple circuit constitution and with high resolution by providing a preliminary integration period before double integral operation and varying the preliminary integration period and each AD conversion period with a series signal having a prescribed factor. CONSTITUTION:A control means 8 controls a switch circuit 4 to apply an input analog signal Ex and a reference voltage Es to an integration device 1 for implementing double integration operation, and a preliminary power supply signal Eb is applied before the inverse integral operation to the double integral operation to execute the preliminary integration operation. Moreover, the control means 8 varies each AD conversion period and the preliminary integral period according to a prescribed series in a range from one to N count pulse by a count means 6 according to a prescribed series. An arithmetic processing means 7 receives a count from the count means 6 to apply an average calculating processing.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a double-integration type A/D converter, and more specifically, to an A/D converter that can achieve high resolution without sacrificing response speed. Regarding D converter.

(Prior Art) FIG. 8 is a block diagram of a conventionally known double integral type A/D converter. In FIG. 0, Sl is an input analog signal E.
A switch I that switches between x and the reference signal Es.
NT is an integrator that integrates the signal taken out by the switch S1, and is composed of a resistor R, a capacitor C1, an amplifier A, and a switch S2 connected in parallel with the capacitor C.

CP is a comparator that compares the output of the integrator with a common potential, and O8 is a tarok oscillator that controls on/off of switches S1 and S2. CU is a counter that counts clocks, and its counting operation is controlled by a signal from the comparator CP. DS is a display device that displays the output of the counter.

The switch S1 first inputs the input signal Ex to the integrator INT for a certain period of time Ts as shown in FIG.

As a result, the output of the integrator INT changes as shown in FIG. 10, and the integrator output Eo after Ts is expressed by equation (1).

Eo= (-Ex/ (C-R))-Ts...
(1) Next, the switch S1 inputs the reference voltage Es to the integrator IN'r' as shown in FIG.

FIG. 10 is a diagram showing changes in the output voltage Eo of the integrator INT, and the integrator output EO at this time is expressed by equation (2).

E o = (-E x / (C-R) l ・T
s+ (Es/ (C-R)l ・t...
- (2) Here, if the time until the output voltage EO becomes zero is TX, then equation (3) is obtained.

Ex= ('r'x/Ts) ・Bs-== (3) Therefore, if the integration time Ts and the reference voltages F and s are constant, the input signal Ex is Tx, that is, the switch S1 is connected to the reference voltage Es side. After that, the output voltage E.

By counting the time until the value becomes zero with the counter CU, a digital signal corresponding to the input analog signal EX can be obtained in the counter.

(Problems to be Solved by the Invention) The A/D converter having such a configuration has characteristics such as that drift of the integral constant CR and the tarokk frequency does not become an error. However, in order to improve the accuracy of A/D conversion,
It is necessary to increase the tarok frequency or increase the integration time.

If the tallock frequency is increased, there is a problem in that high-frequency circuit components must be used, and if the integration time is increased, the response characteristics are deteriorated.

The present invention was made in view of these problems, and
The purpose is to provide high-resolution A/P without compromising response characteristics.
The objective is to realize a D converter with a simple configuration.

(Means for Solving the Problem) FIG. 1 is a basic configuration block diagram of the present invention. In FIG. 0, 1 is an integrator, 2 is a reference power source, 3 is a preliminary integrating power source having a predetermined value, Reference numeral 4 denotes a switch circuit that selects the input analog signal Ex to be converted into a digital signal, the reference voltage ±Es, and the backup power signal Bb, and inputs the selected signals to the integrator 1. 5 is a comparator that receives the output of the integrator 1, 6 is a counting means that receives the signal from the comparator 5, and 7 is an arithmetic processing circuit that receives the counted value from the counting means 6 and performs averaging processing. be.

Reference numeral 8 denotes control means for inputting the signal from the comparator 5 and controlling the switch circuit 4, the integrator 1, and the counting means 6.

(Function) The control means 8 controls the switch circuit 4 to apply the input analog signal Ex and the reference voltage Es to the integrator 1 to perform a double integration operation, and also to perform a double integration operation before the inverse integration operation of the double integration operation. , the control means 8 applies a preliminary power signal Eb and performs a preliminary integration operation, and the control means 8 sets the preliminary integration period in each AD conversion cycle to a range from 1 pulse to N pulses of the counting pulse in the counting means 6. , vary according to a predetermined sequence of numbers.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, parts corresponding to those in FIG. 1 are designated by the same reference numerals. The integrator 1 includes an operational amplifier OP1,
It consists of a capacitor C1 and resistors R3 to R6. The reference voltage source 2 outputs a reference voltage ±Es, and the preliminary integration power source 3 divides the reference voltage −Es by resistors R1 and R2. A microprocessor 9 includes a counter 6 as a counting means, and operates as the arithmetic processing means 7 and the control means 8 in FIG. In addition to the counter 6, the microprocessor 9 includes a clock source 91, an output board 92 that operates in synchronization with the clock from the tarock source 91, and an arithmetic control unit (CPU).
93 and a memory 94.

The operation of the apparatus configured in this way will be explained next.

FIG. 3 is an operation waveform diagram showing an example of the operation. Here, it is assumed that the basic resolution is improved four times, and the resistors R1 and R2 and the integral resistors R4 and R5 that constitute the preliminary integral power supply have the relationships shown in equations (1) to (3). It has become.

R1/ (R1 + R2) = 1/4 (R1: R2 = 3: 1) ...... (1) R1 (R5, R2 (R5 ...... (2) R4 = R5... (3) In Fig. 3, TO is in the initial state, switch SO of switch circuit 4 is on as shown in (a), and capacitor C of integrator 1 is short-circuited. In this state, the output voltage eA of the integrator is approximately OV, and the output voltage eB of the comparator 5 depends on the operational amplifier OPI and the offset voltage of the comparator 5, and is uncertain at both H and L levels.

T1 is a preliminary integration period for high resolution, which is a feature of the present invention. During this period, switch S3
is turned on, and the signal 1 from the preliminary integration power supply 3 is integrated. The integral current value 1 here is expressed by equation (4).

11= (R2/ (R10R2)l X (-Es/
R= (1/4)X (-Es/R5) = (1/4)
The clocks are controlled by the microprocessor 9 according to a predetermined sequence so that the clocks are any one of 1 to 4 clocks of 1 clock) and are evenly distributed over time. More details on this point will be given later.

1 and 2 are other preliminary integration periods, which are not directly related to the present invention, but by providing this period, the input analog signal E
AD conversion is also possible when x takes a negative value. During this pre-integration period, the switch S1 is on as shown in (b), and the integrator 1 integrates the amount of charge shown in equation (5) during that period.

I 2XT2= (Es/R3)XT2・・・・・・(
5) In the next period T3, the input that cancels out this amount of charge is a negative input, and the negative input corresponds to the lower end of the input range of AD conversion.

T3 is an input integration interval. In this section, the switch S4 is turned on as shown in (e), and the current I3 proportional to the input analog signal is integrated for a certain period of time through the resistor R6.

T4 is an inverse integration interval. In this section, switch S
2 is turned on as shown in (C), and the constant current value 4 shown by equation (6) is inversely integrated.

I4= -Es/R4 (6) The operation of the input integral interval T3 and the inverse integral interval 1゛4 is the operation of a -numerical double integral circuit, and the 8th This is similar to the conventional device shown in the figure.

The comparator 5 receives the output voltage eA of the integrator 1 as shown in (f).
and the reference potential are compared and amplified, and as shown in (g), H/
The L digital signal eB is input to the microprocessor 9. The microprocessor 9 receives the digital signal from the comparator 5, generates a timing signal from TO to T4, operates the switch circuit 4, and changes the output eB of the comparator 5 to H from the start of the T4 period. Time up to Tx
is counted by counter 6. As a result, a digital signal corresponding to the input analog signal Ex can be obtained in the counter 6.

The above is an outline of the operation of the apparatus shown in FIG. 2. Next, the operation for achieving high resolution, which is a feature of the present invention, will be explained.

The integral current 11 in the pre-integration period T1 and the integral current I4 in the inverse integration period T4 have a relationship shown by equation (7).

11= (1/4)
Equivalent to 4 clocks.

In FIG. 3, the timing shown by a solid line is T1=1 clock, and the timing shown by a broken line is T1=2 clock. The change timing of the output eB of the comparator 5 is shifted by 1/4 clock for the same input analog signal.

In the present invention, the preliminary integration period T1 provided before the double integration operation is controlled for each AD conversion according to a predetermined numerical sequence so that it varies evenly within the range of 1 to 4 clocks, for example. Then, the output eB of the comparator 5 is evenly distributed at the points when it changes from L to H within the range shown in the variation section of FIG. 4(b).

Therefore, the count value (AD conversion value) of the counter 6 that counts the clock shown in (C) is 1/4 when counted as K, and 3/4 when counted as (K-1).
4 appears.

The arithmetic processing means 7 in the microprocessor 9 averages the count values of the counter 6 to obtain a highly accurate AD conversion value Dx.

That is, according to this example, the average calculation expressed by equation (8) is performed.

Dx= (1/4)xK+ (3/4)X (K-1)
= to - (3/4) (8) By performing such average calculation processing, the resolution of AD conversion can be improved by four times.

Further, in order to obtain four times the resolution, at least four AD conversions are required, but the amount of information up to the basic resolution can be obtained with one AD conversion. Therefore, the AD conversion time can be shortened compared to the conventional method in which high resolution is achieved simply by lengthening the integration time.

The above explanation is based on the assumption that the preliminary integration period T1 provided before the double integration operation is uniformly varied, for example, in the range of 1 to 4 clocks. It is not easy to make the values vary evenly. Using a random number signal may be considered, but in this case, although it is equalized over a long period of time, it will be uneven over a short period of time.

In the present invention, the pre-integration period T1 is uniformly varied from 1 pulse to N pulses of the counting pulse in the counting means.
The range is up to the pulse and is changed according to the sequence a1 that satisfies the following requirements [1] and (2).

[1], the sequence at is 1, 2, 3 . ...i...,n
It consists of n elements consisting of the numerical value of a 1 + a 2
+...an.

Repeat a1, a1, a2,...an...

[2] The number sequence a1 is arranged as large, small, large, small, large, small, etc. with respect to its center value (n±1)/2.

FIG. 5 is a diagram showing an example of the case where n=16 for the sequence a1 that satisfies the above-mentioned requirements [1] and (2). Here ai=il 5,2,11,6°13.4,1
0.7, 16, 1, 12, 5, 14° 3.9.81.

According to such a numerical sequence, by changing the pre-integration period T1 for each A/D conversion in the range from 1 pulse to N pulses of counting pulses in the counting means, the pre-integration period 1.1 is evenly varied. The result is a highly accurate A.
/D conversion value can be obtained.

FIG. 6 is a diagram showing A/D conversion results according to the present invention,
FIG. 7 is a diagram showing the A/D conversion results when a random number signal is used instead of the sequence at used in the present invention.

Here, the preliminary integration period T1 is varied within the range of 1 to 16 pulses of counting pulses in the counting means, and the moving average result of 16 data is used as the average calculation.
/D conversion data Dx.

In the present invention using the sequence ai, there is some deviation after the start until 16 data are taken, but after that, the A/
The D-converted data is stable at a value close to the true value Ds, and a satisfactory result is obtained.

On the other hand, when a random number signal is used, undulations occur around the true value Ds, and good results are not obtained.

(Effects of the Invention) As explained in detail above, according to the present invention, a preliminary integration period T1 is provided before the double integration operation, and this preliminary integration period and each AD conversion period are set to meet predetermined requirements. The change is made by a sequence signal, and a high-resolution digital signal can be obtained with a simple circuit configuration without increasing the AD conversion time.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration block diagram of the present invention, FIG. 2 is a configuration block diagram showing an embodiment of the present invention, and FIGS.
The figure is a waveform diagram for explaining its operation, FIG. 5 is a diagram showing an example of a sequence signal used in the present invention, FIG. 6 is a diagram showing A/D conversion results according to the present invention, and FIG. 7 is a diagram showing the present invention. A/D when a random number signal is used instead of the number sequence signal according to the invention
FIG. 8 is a block diagram of the configuration of the conventional device, and FIGS. 9 and 10 are diagrams showing its operation waveforms. 1... Integrator 2... Reference power supply 3... Reserve integration power supply 4... Switch circuit 5... Comparator 6... Counting means 7... Arithmetic processing means 8... Control means 9...to microprocessor■ G) riO ku-X -1→shi

Claims (1)

[Claims] An integrator, a reference power source, a backup integrating power source that outputs a voltage at a predetermined ratio with respect to the reference power source voltage, and an input analog signal, a reference signal, and a backup power source signal that are selected and sent to the integrator. a switch circuit for input, a comparator for inputting the output of the integrator,
a counting means for inputting the signal from the comparator, an arithmetic processing circuit for inputting the counted value from the counting means and performing an average calculation process, and the switch circuit, the integrator, and the counting means for inputting the signal from the comparator. and a control means for controlling a switch circuit to apply an input analog signal and a reference signal to an integrator to perform a double integral operation, and to perform an inverse integral operation of the double integral operation. Previously, a preliminary power supply signal is applied, a preliminary integration operation is performed, and each A/D conversion period and preliminary integration period is in the range of 1 pulse to N pulses of counting pulses in the counting means, and the following requirements [ 1], [2
] An A/D converter characterized in that the A/D converter changes according to a sequence ai that satisfies the following. [1] The sequence ai is 1, 2, 3,...i...,n
Consists of n elements consisting of numerical values, a1, a2,...
Repeat an, a1, a2,...an... [2] The sequence ai is arranged as large, small, large, small, large, small, etc. with respect to its center value (n+1)/2.