JPH02196523A - Test circuit for delta sigma modulation type a/d converter - Google Patents

Abstract

PURPOSE:To test the operation of a delta sigma modulation type A/D converter with high accuracy by applying gate control to the output pulse of the delta sigma modulation type A/D converter and allowing a counter to count the pulse. CONSTITUTION:A timing control means 23 controls the timing of a counting means 21 and a latch means 22, receives the output of a delta sigma modulation type A/D converter 10 and the counter means 21 converts the output into a pulse number in response to the level of an analog input. The output of the counting means 21 is held once in the holding means 22 and the result is extracted as a digital output. Thus, the operation of the delta sigma modulation type A/D converter 10 is checked digitally to attain an accurate test.

Description

[Detailed Description of the Invention] [Summary] A test circuit for a ΔΣ modulation type A/D converter for testing whether the operation of the ΔΣ modulation type A/D converter is normal; A counting means for counting the output of the ΔΣ modulation type A/D converter for the purpose of accurately testing the operation of the converter;
It is composed of a holding means for holding the output of the counting means, and a timing control means for controlling the timing of these counting means and the holding means, and is configured to take the output of the holding means as its output.

[Field of Industrial Application] The present invention relates to a testing circuit for a ΔΣ modulation type A/D converter for testing whether the operation of the ΔΣ modulation type A/D converter is normal.

A/D to convert analog signals to digital data
A converter is used. The operating methods of this A/D converter are an integral method and a successive approximation method.

Various methods such as ΔΣ modulation method are possible. These A
Among the A/D conversion methods, the ΔΣ modulation type A/D conversion method outputs pulses proportional to the input and is not directly output, so the problem is how to accurately test the operation of the A/D converter. becomes.

[Prior Art] FIG. 5 is a diagram showing the configuration principle of a conventional ΔΣ modulation type A/D converter. The analog input S (t) enters the arithmetic unit 1, and subtraction is performed between it and the feedback signal 1 (t),
The calculation result d (t) -8 (t) p - (t) is integrator 2
and is integrated. The integration result ε(1) is entered into a comparator 3, compared with a reference value, and converted into binary data of ±1. In this sense, comparator 3 can also be regarded as a 1-bit A/D converter. The output of this comparator 3 becomes a digital output p (t), which is input to a 1-bit D/A converter 4 and converted into an analog signal.
It enters the arithmetic unit 1 as the feedback signal p-(t).

FIG. 6 is an explanatory diagram of the operation of the ΔΣ modulation type A/D converter.

(A) is the analog input S (t), and as shown in the figure, -FS (full scale) is set at a predetermined interval (the horizontal axis indicates time).
It varies from 10FS (full scale) to 10FS (full scale). On the other hand, (b) shows the digital output P (t), which, as shown in the figure, is output as a pulse sequence of a 1-bit digital signal depending on the input terminal level.

In the output of this type of ΔΣ modulation type A/D converter, the number of pulses in a constant time corresponds to the input level. for example,
When a direct current with a negative FS is applied to human power, the output of the ΔΣ modulation type A/D converter is a continuous logical value “0”, and a positive F
When a direct current of S is input, the output of the ΔΣ modulation type A/D converter is a continuous logical value “1”. If you input the center value of positive and negative FS (that is, 0), “0” will be displayed as shown in the figure.
and "1" are output alternately and continuously.

When testing the operation of a ΔΣ modulation type A/D converter having such characteristics, a test circuit as shown in FIG. 7 is used. In the figure, numeral 10 is a ΔΣ modulation type A/D converter to be tested, which is operated by a clock fs. An arbitrary DC voltage is input to this ΔΣ modulation type A/D converter 10 from a variable output DC power supply 11 . This Σ modulation type A/D converter 10 outputs bit-serial pulses according to the input, which enters an RC filter 12 consisting of a resistor R and a capacitor C, and are converted into a flat DC level. This DC level is read on a subsequent voltmeter.

[Problems to be solved by the invention] In the case of the analog test method as described above, although the circuit configuration is simple, the accuracy of the RC filter is not good, and the CR time constant changes due to power supply fluctuations, temperature fluctuations, etc. In addition, there was a problem with the stability of the DC level due to the duty fluctuation rate of the output pulse, etc., and accurate testing was not possible. Another problem is that the higher the input frequency, the more its components are bypassed via the capacitor C, resulting in a lower output level.

The present invention has been made in view of such problems, and provides a test circuit for a ΔΣ modulation type A/D converter that can accurately test the operation of the ΔΣ modulation type A/D converter. It is an object.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. Components that are the same as those in FIG. 7 are shown with the same reference numerals hidden. In the figure, 10
is the Δ that receives analog input and converts it to digital data.
Σ modulation type A/D converter (target to be inspected); 21 is a counting means for counting the output of the ΔΣ modulation type A/D converter 10; 22;
2 is a holding means for holding the output of the counting means 21, and 23 is a timing control means for controlling the timing of the counting means 21 and the holding means 22.

[Function] The timing control means 23 controls the timing of the counting means 21 and the holding means 22, and upon receiving the output of the ΔΣ modulation type A/D converter 10, the counting means 21 adjusts the number of pulses according to the level of analog human power. Convert. The output of the counting means 21 is temporarily held in the holding means 22 and taken out as a digital output. According to the present invention, the ΔΣ modulation type A/D
The operation of the transducer 10 can be checked digitally, thus allowing accurate testing.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. Components that are the same as those in FIG. 1 are designated by the same reference numerals. In the figure, 24 receives the output of the ΔΣ modulation type A/D converter 10 and the clock [S, creates a gate width according to the analog human power level, passes the clock fs within the gate width, and outputs the clock fs. 21 is a gate control circuit.

Here, a counter is used as the counting means 21, and a register is used as the holding means 22. The operation of the circuit configured as described above will be explained below with reference to the timing chart shown in FIG.

First, it is assumed that +FS is included in the circuit shown in FIG.

The output of the ΔΣ modulation type A/D converter 10 at this time is shown in Figure 3 (
As shown in b), it remains at the "1" level. When the gate control circuit 24 receives this constant "1 level signal,"
Count the lock fs for a predetermined period as shown in (
A counter input g as shown in c) is given to the counter 21. As a result, the counter 21 counts the full number of clocks and causes the register 22 to hold the counted clocks.

On the other hand, it is assumed that -FS is included in the human power. ΔΣ at this time
The output of the modulation type A/D converter 10 remains at the "0° level" as shown in FIG. 3(d).

When the gate control circuit 24 receives this constant "0" level signal, it causes the lock f8 to count for a predetermined period as shown in (B) and provides the counter input g as shown in (E) to the counter 21. As a result, the counter 21 counts the full number of clocks and causes the register 22 to hold the counted clocks.

Furthermore, it is assumed that 0 is entered in the input. At this time, ΔΣ
The output of the modulation type A/D converter 10 is a pulse in which positive and negative pulses are alternately output as shown in (v). In response to such a pulse, the gate control circuit 24 outputs a pulse as shown in (g) to mask the pulse shown in (f), thereby preventing the clock from being output. As a result, the counter force g is, as shown in (H), since the clock does not appear.
The count value of the counter 21 becomes zero. In the above, cases where the analog input is +FS, -FS, and 0 have been explained, but the gate control circuit 24 also applies when the input takes an intermediate value.
performs gate control, outputs as many clocks as the number of inputs, and supplies them to the counter 21. In this way, according to the present invention, a ΔΣ modulation type A/D converter can be tested with high precision.
It can be done with high resolution.

FIG. 4 is an explanatory diagram of the operation of a test circuit for a ΔΣ modulation type A/D converter according to the present invention. In the figure, (a) is the output j1 of the ΔΣ modulation type A/D converter 10 (b) is the output of the counter 21, and (c) is the output of the counter 2 from the timing control circuit 23.
(d) is the counter clear signal S2 which is also given to the counter 21 from the timing control circuit 23, and (e) is the register latch signal given to the register 22 from the timing control circuit 23. (f) is the contents of the register 22.

The pulses shown in (a) are transmitted to the ΔΣ modulation type A/D converter 1.
When 0 is output, the output of the counter 21 increases sequentially as shown in (b), and the counter clear signal S2 shown in (d) is generated.
It will be cleared when it is output. Immediately before this counter clear signal S2 is output, a register latch signal shown in (E) is output to the register 22, and the count value of the counter 21 immediately before being cleared is taken into the register 22.

The captured data becomes output 0. The counter 21 starts counting the output of the ΔΣ modulation type A/D converter 10 again from the moment it is cleared to 0.

[Effects of the Invention] As described above in detail, according to the present invention, by adopting a configuration in which the output pulse of the ΔΣ modulation type A/D converter is gate-controlled and then counted by the counter, the output pulse of the ΔΣ modulation type A/D converter is gate-controlled. It is possible to provide a test circuit for a ΔΣ modulation type A/D converter that can accurately test the operation of the A/D converter.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a configuration block diagram showing an embodiment of the present invention, Fig. 3 is a timing chart showing the operation of each part, and Fig. 4 is a ΔΣ modulation type A according to the present invention. /D converter test circuit operation diagram; Figure 5 is a configuration principle diagram of a ΔΣ modulation type A/D converter; Figure 6 is a diagram explaining the operation of a ΔΣ modulation type A/D converter; Figure 7 1 is a diagram showing an example of a conventional test circuit. In FIG. 1, 10 is a ΔΣ modulation type A/D converter, 21 is a counting means, 22 is a holding means, and 23 is a timing control means. (a) Input + output at FS j (b) Clock fs (c) Counter input! (e) Counter input! [Former ■■m f-o ■■ Publication 4

Claims (1)

[Claims] Counting means (21) for counting the output of the ΔΣ modulation type A/D converter (10), and holding means (22) for holding the output of the counting means (21).
and a timing control means (23) for controlling the timing of the counting means (21) and the holding means (22), and a ΔΣ modulation type A/D conversion whose output is the output of the holding means (22). instrument test circuit.