GB2227381A

GB2227381A - Analogue to digital converters

Info

Publication number: GB2227381A
Application number: GB8823589A
Authority: GB
Inventors: Kenneth Robert Dickson; Timothy Robert Joyce
Original assignee: General Electric Co PLC
Current assignee: General Electric Co PLC
Priority date: 1988-10-07
Filing date: 1988-10-07
Publication date: 1990-07-25
Also published as: GB8823589D0

Abstract

An analogue to digital converter arrangement includes an analogue to digital converter (5); means (1, 3) for applying to the converter a succession of pairs of signals, each of which pairs comprises a first analogue signal representative of the sum of a sample of an analogue input signal (Vin) required to be converted to a digital signal by the arrangement and a sample of a periodically varying signal (R), and a second analogue signal representative of the sample of the periodically varying signal (R); means (7, 9, 11) for deriving in respect of each said pair of signals a difference digital signal equal to the difference of the two digital signals appearing at the output of the converter in response to that pair of signals; and means (15) for producing a digital output signal which is the average of a predetermined plurality (X) of successive said difference digital signals. The arrangement produces an output of higher resolution than that of which the A/D converter (5) of the arrangement is capable. <IMAGE>

Description

Analogue-to-digital converters This invention relates to analogue-to-digital (A/D) converters.

More particularly the invention relates to A/D converter arrangements of the kind wherein a varying signal is added to the input signal of an A/D converter and the digital output of the converter is averaged over a period to obtain a digital signal corresponding to the input signal of the converter to a higher resolution than the output of the converter.

In known such arrangements the varying signal, cornonly called a 'dither' signal, is a periodic signal whose amplitude necessarily exceeds the quantisation step of the converter and whose frequency is necessarily less than the sampling frequency of the converter.

Known such arrangements have used a 'dither' signal of frequency higher than that of the signal of interest i.e. the input signal of the arrangement.

It is an object of the present invention to provide an A/D converter arrangement employing the 'dither' signal technique for increasing resolution wherein the 'dither' signal may have a frequency lower than that of the signal of interest.

According to the present invention there is provided an AID converter arrangement comprising: an A/D converter; means for applying a succession of analogue input signals to the converter, said succession comprising successive pairs of signals, each of which pairs comprises a first analogue signal representative of the sum of a sample of an analogue input signal of the arrangement and a sample of a periodically varying signal and a second analogue signal representative of said sample of said periodically varying signal; means for deriving in respect of each said pair of signals a difference digital signal equal to the difference between the two digital signals appearing at the output of the converter in response to said pair of signals; and means for producing a digital output signal which is the average of a predetermined plurality of successive said difference digital signals or a function thereof.

Where the digital output signal is the average of a function of said predetermined plurality of successive said difference digital signals, said function is preferably obtained by processing said difference digital signals before averaging.

In one such arrangement said succession comprises successive first said pairs of signals in respect of a first analogue input signal of the arrangement and successive second said pairs of signals in respect of a second analogue input signal of the arrangement, and said digital output signal is the average of a predetermined plurality of digital signals each of which comprises the product of a first said difference digital signal produced using a first said pair of signals and a second said difference signal using a second said pair of signals, so that said digital output signal is a digital signal representative of the product of said first and second analogue input signals of the arrangement.

Two A/D converter arrangements in accordance with the invention and modifications of the two arrangements will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1 is a block schematic diagram of the first arrangement; Figure 2 illustrates a modification of the arrangement of Figure 1; Figure 3 is a block schematic diagram of the second arrangement; Figure 4 illustrates a first modification of the arrangement of Figure 3; and Figure 5 illustrates a second modification of the arrangement of Figure 3.

Referring to Figure 1, the first arrangement includes a multiplexer 1 which during alternate ones of successive periods Tc/2 outputs an analogue voltage Vin which it is desired to convert to a digital signal, and during the other periods outputs zero volts or ground potential (GND). The output of the multiplexer 1 is applied to one input of an adder 3 to the other input of which there is applied a periodically varying signal R. The output of the adder 3, which comprises alternately in sequence the analogue sum of Vin and R and R alone, is applied to the input of an A/D converter 5. The A/D converter 5 samples its input at a frequency 2Fc (where Fc = 1/Tc) to produce alternately in sequence digital outputs representing the sum of Vin and R, and R alone.

The converter 5 is typically arranged to operate with a unipolar input voltage in which case the signal R suitably has a peak-to-peak amplitude of one quarter of the full-scale input voltage of the converter 5 and a mean value equal to half the full-scale input voltage. The signal R typically is of sinewave, sawtooth or triangular waveform and has a period determined by the rate at which signal Vin is sampled (Fc) and the desired resolution of the digital output of the arrangement, as further explained below. It will be understood that in other arrangements in accordance with the invention the converter 5 may be arranged to operate with a bipolar input voltage.

It will be appreciated that the resolution of the converter 5 is coarser than the desired resolution of the output of the arrangement, and is typically of 8 bits. The converter sampling frequency 2Fc is chosen so as to result in over-sampling input signal Yin and for an 8 bit successive approximation converter is typically in the range 10 kHz to 100 kHz, the input signal Vin typically having a frequency one-tenth to one-twentieth of Fc or less, depending on the required resolution.

The output of the converter 5 is applied to a differencing circuit 7 via latches 9 and 11, the converter output corresponding to input Vin + R being stored in latch 9 and the converter output corresponding to input R being stored in latch 11. At the end of each period Tc a digital signal equal to the difference of Vin + R and R appears at the output of the circuit 7. It will be appreciated that this digital signal is of the same resolution as the output of the converter 5.

The operation of latches 9 and 11 in sequence is controlled by a control circuit 13 which also divides the control frequency 2Fc for use in a further circuit 15, described below.

The signal appearing at the output of differencing circuit 7 at the end of each period Tc is applied to the circuit 15 which produces a digital signal which is the average of X successive signals at the output of circuit 7. To this end the circuit 15 comprises an accumulator 17, a divider 19 and a counter 21.

The accumulator 17 sums the data at the output of differencing circuit 7. Counter 21 counts to a predetermined number X of clock pulses of frequency Fc applied to it from control circuit 13, and at this instant the output of accumulator 17 is transferred to the input of divider 19 which divides the accumulator output by X, the resulting signal N out at the output of divider 19 constituting the output of the arrangement.

Transfer of the accumulated signal is accompanied by resetting the accumulator 17 and the counter 21 to zero for the next accumulation and divide sequence.

Where Do equals the number of bits in each output of the converter 5, and hence in each output of the differencing circuit 7, the number of bits in the output signal N out is Do + Dr where the maximum value of Dr is calculated from the ratio of the rate of sampling of Vin to the rate at which the accumulator 17 is read and reset. Thus the maximum value of Dr = log2 (Fc/Fc/X) = log2X.

Hence where Do = 8 and a resolution of 12 bits is required in N out, Dr = 4 and X = 16.

The signal R is required to vary so that the values of R used during each accumulation period vary in an indeterminate manner, that is to say a random manner, with respect to the sampling of the input signal Vin, and so that R varies through a range greater than the quantisation level of the converter.

However, there is no requirement for R to vary through an integral number of full cycles during each accumulation period. Thus R may be arranged to change relatively slowly compared with the rate of change of R required in known arrangements for increasing resolution of an A/D converter using the 'dither' signal technique.

Consequently, possible errors arising from differences in time of sampling R and Vin are reduced.

It will be appreciated that the part 23 of the arrangement after the converter 5, although shown in Figure 1 as comprising discrete components 7 to 21, may suitably be constituted by an appropriately programmed microprocessor.

One application of the arrangement of Figure 1 is the measurement of the level of a d.c. signal voltage (Vin).

Alternatively the arrangement of Figure 1 may be used to measure the level of a varying signal voltage over a small portion of its waveform, i.e. during the time the signal voltage is being sampled.

Referring now to Figure 2, in a modification of the arrangement of Figure 1 to enable any selected one of a plurality of analogue input signals V1 to Vn to be converted to a digital signal, the input stages 1, 3 of the Figure 1 arrangement, are replaced by multiplexer 25 whose output is connected to the input of the converter 5, and a plurality of two input adders 27 whose outputs are applied to respective inputs of the multiplexer 25 and whose two inputs each comprise a respective one of the input signals V1 to Vn and the signal R. The signal R is also applied alone to a further input of the multiplexer 25.The multiplexer 25 is operated at a frequency Fc to apply alternately to the input of the converter 5 the R input and an input comprising the sum of the selected input V1 to Vn and signal R.

Where a digital output is required which is a function of one or more analogue input signals, an arrangement according to the invention wherein the required function is obtained using the A/D converter outputs, i.e. before averaging of successive converter digital outputs, may be used.

One such arrangement will now be described by way of example.

The arrangement produces a digital output, to a higher resolution than that given by the output of the A/D converter used in the arrangement. The arrangement has two input signals related to the power dissipated in a load connected to an a.c. mains supply, e.g. inputs respectively proportional to the current drawn by the load and the voltage drop across the load. The arrangement gives an output which is representative of the electric power consumed in the load. The arrangement measures the mean of the product of the two input signals, i.e. the average power over a period. The instantaneous power is not measured to a high resolution.

Referring now to Figure 3, the arrangement comprises an A/D converter 31 whose input is derived by way of a multiplexer 33 and two adder circuits 35 and 37, in an arrangement similar to that shown in Figure 2, so as to comprise any selected one of three analogue input signals Vin + R, Iin + R and R, where R is a periodically varying signal derived from a generator 39 and Vin and Iin are respectively signals representing the voltage and current supplied to the load (not shown).

In an alternative arrangement, shown in Figure 4, the required inputs for the converter 31 may be produced by using a multiplexer 41 to apply any selected one of signals Vin, lin and a zero reference signal Vz to a first input of a two-input adder circuit 43 to whose other input the signal R is applied, the output of the adder 43 being utilised as the input to the converter 31.

Each output of the converter 31 is stored in a selected one of three latch circuits 45, 47 and 49 under control of a latch control circuit 51 according to whether the output corresponds to input Vin + R, lin + R or R.

The multiplexer 33, converter 31 and latch control circuit 51 are operated at a frequency 3Fc by pulses derived from a clock generator 53 to produce in sequence at the output of the converter, and hence to hold in the latch circuits 45, 47 and 49, digital signals which are respectively representative of Vin + R, R and Iin + R. The frequency Fc is chosen to suit the sampling method adopted, which in turn depends on the possible harmonic content of the input signals Vin and Iin, and the processing to be carried out after A/D conversion, as hereafter described. The sampling method may, for example, comprise sampling at a rate such that both Vin and Iin are sampled at a frequency at least twice the frequency of the highest frequency component of interest in Vin and Iin.

Alternatively a slipping sampling technique may be adopted which allows a representative sampling of the Vin and Iin waveforms over a number of cycles of the waveform if the Vin and Iin waveforms maintain constant amplitude, frequency and relative phase over the sampling period.

The signals held in latch circuits 45 and 47 are respectively applied to the inputs of a differencing circuit 55 to produce a digital signal V representative of Vin, the signal V being applied to one input of a multiplier 57. Similarly the signals held in latch circuits 47 and 49 are respectively applied to the inputs of differencing circuit 59 to produce a digital signal I representative of Iin, the signal I being applied to a second input of the multiplier 57.

The multiplier 57 thus produces an output digital signal VI representative of the instantaneous power supplied to the load, the signal VI being updated at a frequency Fc. It will be understood that the signal VI comprises more bits than the input signals to the multiplier 57 although it is not of course of greater resolution.

Each discrete set of X successive digital signals VI at the output of the multiplier 57 is summed In an accumulator 61, operated under control of clock pulses of frequency Fc derived from generator 53 via a timing control generator 63, and being reset after each set of X signals at the output of multiplier 57 by pulses of frequency Fc/X derived from the output of the timing control generator 63 by way of a frequency divider circuit 65.

The output of the accumulator 61 is sampled by a sampling circuit 67 at a rate Fc/X under control of clock pulses derived from divider circuit 65 to provide a series of digital signals representative of the average of the multiplier output signals VI, which series constitutes the output of the arrangement. The relationship between the slew rate of R and the sampling rate Fc of each input determines the minimum residual error (i.e. minimum fluctuation of the output with a full scale input).

The part 69 of the arrangement after the converter 31, although shown in Figure 3 as comprising discrete components 45 to 67, may suitably be constituted by an appropriately programmed microprocessor.

It will be appreciated that each output of the arrangement represents the average power consumed in the load over the preceding period of accumulation of the accumulator circuit 61, to a resolution increased over the resolution of the output of the converter 31 by a number of bits Dr where Dn = Di + Dr, Di is the number of bits in the output of the converter and Dn is the number of bits in the output of the sampler 67, Dout.

Dr is determined by the ratio of the sampling rate Fc of the input signals Vin and In and the reset rate Fc/X of the accumulator 65. More specifically Dr = log2 Fc/3 = log2 X Fc/3X It will be understood that Dn is not necessarily equal to the number of bits Da in the output of the accumulator 61. In this case the bits Dl remaining in the accumulator after removal of the Dn bits constituting the arrangement output may be dumped to a register (not shown) to enable separate calculation of average power over the accumulation period and the total power over a longer period of time.

It will be appreciated that accuracy of the output of the arrangement is affected by differences in times of sampling of the Vin, In and R components of the data applied to differencing circuits 55 and 57.

To reduce this problem alternative sampling sequences to the simple repetitive sampling of Vin + R, R, In + R in turn described above may be used.

For example the sampling sequence may comprise obtaining samples of Vin + R, R, In + R, R in turn, and using the first two samples in each such sequence to obtain V and the last two to obtain I.

This improves the accuracy of V and I but can still give rise to inaccuracy of power measurement due to time lag between sampling Vin + R and In + R.

This time lag can be reduced by using the sampling sequence Vin + R, In + R, R, Vin + R or Vin + R, R, In + R, Vin + R and using the first and last samples to obtain a value for Vin + R approximating in time to the In + R sample e.g. by obtaining the arithmetic mean of the first and last samples. A similar procedure may be adopted using the sequence In + R, Vin + R, R, In + R or In + R, R, Vin + R, In + R.

A further possibility is to use the sampling sequence Vin + R, R, In + R, R, Vin + R, or Iin + R, R, Vin + R, R, In + R obtaining first values Y1, I1 for V and I using the first three samples and obtaining second values V2, 12 for V and I using the last three samples. The products V1.11 and V2.I2 are then both obtained and accumulated in accumulator 61 and the output of the accumulator halved to give the required power measurement.

An alternative solution to this time lag problem is to produce the inputs for the A/D converter 31 using an arrangement as shown in Figure 5 which is essentially as shown in Figure 3, but with a sample and hold circuit 71, 73 or 75 in each input to the multiplexer 33. In operation of this arrangement the sample and hold circuits 71, 73 and 75 are controlled so as to sample Vin, R and In simultaneously and hold the sampled signals for subsequent supply to the multiplexer 33 and hence to the A/D converter 31 so that each digital signal VI at the output of multiplier is produced using values of Vin, In and R relating to the same instant in time.

Claims

1. An A/D converter arrangement comprising: an A/D converter; means for applying a succession of analogue input signals to the converter, said succession comprising successive pairs of signals, each of which pairs comprises a first analogue signal representative of the sum of a sample of an analogue input signal of the arrangement and a sample of a periodically varying signal and a second analogue signal representative of said sample of said periodically varying signal; means for deriving in respect of each said pair of signals a difference digital signal equal to the difference between the two digital signals appearing at the output of the converter in response to said pair of signals; and means for producing a digital output signal which is the average of a predetermined plurality of successive said difference digital signals or a function thereof.

2. A converter arrangement according to Claim 1 wherein said digital output signal is the average of a function of said predetermined plurality of successive said difference digital signals obtained by processing said difference digital signals before averaging.

3. A converter arrangement according to Claim 2 wherein said succession comprises successive first said pairs of signals in respect of a first analogue input signal of the arrangement and successive second said pairs of signals in respect of a second analogue input signal of the arrangement, and said digital output signal is the average of a predetermined plurality of digital signals each of which comprises the product of a first said difference digital signal produced using a first said pair of signals and a second said difference signal using a second said pair of signals, so that said digital output signal is a digital signal representative of the product of said first and second analogue input signals of the arrangement.

4. A converter arrangement according to Claim 3 wherein said succession of input signals to the converter comprises a repeating sequence of signals A + R, R, B + R where A and B are respectively said first and second analogue input signals of the arrangement and R is said periodically varying signal, and for each said sequence a said first said difference digital signal is produced using digital signals corresponding to the first and second signals of the sequence, a said second said difference signal is produced using digital signals corresponding to the second and third signals of the sequence.

5. A converter arrangement according to Claim 3 wherein said succession of input signals to the converter comprises a repeating sequence of signals A + R, R, B + R, R or R, A + R, R, B + R where A and B are respectively said first and second analogue input signals of the arrangement and R is said periodically varying signal, and for each said sequence a said first said difference digital signal is produced using digital signals corresponding to the first and second signals of the sequence and a said second said difference digital signal is produced using digital signals corresponding to the third and fourth signals of the sequence.

6. A converter arrangement according to Claim 3 wherein said succession of input signals to the converter comprises a repeating sequence of signals A + R, B + R, R, A + R or A + R, R, B + R, A + R where A and B are respectively said first and second analogue input signals of the arrangement and R is said periodically varying signal, and for each said sequence a said first said difference digital signal is produced using digital signals corresponding to the first and last and the R signals of the sequence, and a said second difference digital signal is produced using the second and third signals of the sequence.

7. A converter arrangement according to Claim 3 wherein said succession of input signals to the converter comprises a repeating sequence of signals A + R, R, B + R, R, A + R where A and B are respectively said first and second analogue input signals of the arrangement and R is said periodically varying signal, and for each said sequence, first and second said difference digital signals are produced using the first three signals of the sequence, and first and second said difference digital signals are produced using the last three signals of the sequence.

8. A converter arrangement according to any one of Claims 3 to 7 including latching means between the output of said converter and said means for deriving a difference digital signal, which latching means serves to latch separately outputs of the converter corresponding to different inputs of the converter.

9. A converter arrangement according to any one of Claims 3 to 8 wherein said first and second analogue input signals of the arrangement represent the voltage and current supplied to a load so that the digital output signal represents the power supplied to the load.

10. A converter arrangement according to any one of the preceding claims wherein said means for applying a succession of analogue input signals to the converter comprises: at least one adder circuit having a first input to which an analogue input signal of the arrangement is applied and a second input to which said periodically varying signal is applied, and a multiplexer means having a first input to which said periodically varying signal is applied, a second input connected to the output of said adder circuit, and an output connected to the input of the converter.

11. A converter arrangement according to Claim 10 wherein a sample and hold circuit is provided in each input to the multiplexer means, the sample and hold circuits being operated so that each said difference digital signal is produced using values of the input signals to the multiplexer means relating to the same instant in time.

12. A converter arrangement according to any one of Claims 1 to 9 wherein said means for applying a succession of analogue input signals to the converter comprises a multiplexer means having a first input to which a zero reference signal is applied and at least one further input to which an analogue input signal of the arrangement is applied, and an adder circuit having a first input to which the output of the multiplexer means Is applied, a second input to which said periodically varying signal is applied and an output connected to the input of the converter.

13. An A/D converter arrangement substantially as hereinbefore described with reference to the accompanying drawings.