JPH0530085B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital filter that obtains a binary output digital signal by adding frequency characteristics to a binary input digital signal.

Conventional configurations and their problems Recently, the digitalization of home VTRs, especially the servo system, has been active, and digital servo systems have already been developed.
It has been commercialized and introduced as an IC (integrated circuit). The aim of this digitalization is to reduce the number of adjustment parts and peripheral parts, reduce power consumption, improve reliability, and support multi-functionality, and a fairly large scale digitalization is being planned. However, the phase compensation circuit (hereinafter referred to as a filter) that determines the characteristics of the servo system
At present, however, it still consists of a resistor and a large electrolytic capacitor.

As a conventional example of such a filter, an analog integration circuit is shown in FIG. FIG. 2 is a waveform diagram for explaining the operation.

The components of the analog integrating circuit are an operational amplifier 1, an input resistor 2, and a feedback capacitor 3. now,
When a potential difference occurs between input voltages E ₁ and E ₂ , input resistance 2
A current flows through the capacitor 3, and the output voltage E ₀ changes. The potential of the output voltage E ₀ drops when E ₁ > E ₂ (~t ₁ , t ₄ , ~ t ₅ ), and stops when E ₁ = E ₂ (t ₁ ~ _{t 2} , t ₅ ~ ), and has the characteristic that when E ₁ < E ₂ , the potential increases (t ₂ to _{t 3} ). The transmission relationship G(s) of this circuit is G(s)=1/ST ₁ ...(1) However, T ₁ = C ₁ R ₁ , C ₁ is the capacitance of the feedback capacitor 3, and R ₁ is the input resistance 2. is the resistance value of That is, it functions as an integral element.

In Figure 3, a feedback resistor 4 is added to the components in Figure 1, and the transfer function G(s) is G(s) = 1 + sT ₂ /ST ₁ ... (2) However, T ₁ = C ₁ R ₁ , T ₂ = C ₂ R ₂ , R ₂ is feedback resistance 4
is the resistance value of When formula (2) is transformed, it becomes G(s)=1/ST ₁ +T ₂ /T ₁ (3), which has an integral element and a proportional element. Note that since the magnitude of the current flowing through the input resistor 2 is proportional to the potential difference between the input voltages E ₁ and E ₂ , charging and discharging of the charge in the feedback capacitor 3 is also proportional. However, the slope of the potential of the output voltage E ₀ shown in FIG. 2 is E ₁ , E ₂
It changes in proportion to the potential difference between.

In addition, in the specific circuit examples shown in FIGS. 1 and 3,
Input voltage E ₁ is an input analog signal, input voltage E ₂ is a reference analog signal, output voltage E ₀ is an output analog signal, and the output analog signal is a signal with integral or proportional integral characteristics added to the input analog signal. .

When integrating the integral circuit in Figure 1 and the proportional + integral circuit in Figure 3 explained above, the number of input/output pins of operational amplifier 1 is three, and two to three external CR components are required.
There was a problem that the number of external parts and pins could not be reduced.

Purpose of the Invention The present invention solves the above-mentioned conventional problems.
The object of the present invention is to provide a digital filter in which all components are digitized.

Structure of the Invention The present invention includes a reference signal generating means for generating and outputting an N-bit (N is a natural number) reference digital signal, and a means for comparing the N-bit input digital signal with the reference digital signal to determine the magnitude thereof. a size determining means for outputting a first switching signal representing "large" and a second switching signal representing "small"; gate means for gating and outputting the two switching ^signals respectively; a frequency dividing means for outputting a number of pulses proportional to the absolute value of the difference between the input digital signal and the reference digital signal for each unit period, with a period being a unit period; and two switching via the gate means. reversible counting means that switches an up counting direction on one side of the signal and switches a down counting direction on the other side, and counts the output of the frequency dividing means to obtain an output digital signal of M bits (M is a natural number); a first detection means that detects the maximum value of the reversible counting means to obtain a first detection signal, and receives the minimum value of the reversible counting means as an input to the gate means for gating one of the two switching signals; a second detection signal, the second detection signal being input to said gating means for gating the other of said two switching signals;
This digital filter is characterized in that it is equipped with a detection means, and a digital integration circuit can be realized with a relatively simple configuration.

The present invention also provides a reference signal generating means for generating and outputting an N-bit (N is a natural number) reference digital signal, and a means for comparing the N-bit input digital signal with the reference digital signal to determine whether it is large or small. ”
large/small discrimination means for outputting a first switching signal representing "small" and a second switching signal representing "small"; gate means for gating and outputting the two switching signals respectively _; a frequency dividing means for outputting a number of pulses proportional to the absolute value of the difference between the input digital signal and the reference digital signal for each unit period; and two switching signals via the gate means. Switching the up counting direction on one hand, switching the down counting direction on the other hand, and counting the output of the frequency dividing means,
reversible counting means for obtaining a digital output of M bits (M is a natural number); and gate means for detecting the maximum value of the reversible counting means to obtain a first detection signal and gating one of the two switching signals. a first detection means as an input; and a second detection means that detects the minimum value of the reversible counting means to obtain a second detection signal and serves as an input to the gate means for gating the other of the two switching signals; , comprising a multiplication means for multiplying the input digital signal by a coefficient, and an addition or subtraction means for adding or subtracting the output of the reversible counting means and the output of the multiplication means to obtain an output digital signal. It is a digital filter that can realize a digital proportional-integral circuit with a relatively simple configuration.

The present invention also provides a reference signal generating means for generating and outputting an N-bit (N is a natural number) reference digital signal, and a means for comparing the N-bit input digital signal with the reference digital signal to determine whether it is large or small. ”
a first switching signal representing "small" and a second switching signal representing "^small"; frequency dividing means for outputting a number of pulses proportional to the absolute value of the difference from the reference digital signal; gate means for gating and outputting the output of the frequency dividing means; and counting for one of the two switching signals. reversible counting means which switches the direction of counting, on the other hand switches the down counting direction, and coefficients the output of the gate means to obtain an output digital signal of M bits (M is a natural number); and a maximum value of the reversible counting means. The gate means includes a first detection means for detecting the first detection signal and a second detection type stage for detecting the minimum value of the reversible counting means and obtaining a second detection signal, and the gate means is configured to detect the second detection signal. The logical product of one of the two switching signals and the first detection signal, the logical product of the other of the two switching signals and the second detection signal, and the logical sum of the two logical product outputs are calculated. The present invention is a digital filter characterized in that the output of the frequency dividing means is gated by the output of the frequency dividing means, and a digital integration circuit can be realized with a relatively simple configuration.

The present invention also provides a reference signal generating means for generating and outputting an N-bit (N is a natural number) reference digital signal, and a means for comparing the N-bit input digital signal with the reference digital signal to determine whether it is large or small. ”
a first switching signal representing "small" and a second switching signal representing "_small"; frequency dividing means for outputting a number of pulses proportional to the absolute value of the difference from the reference digital signal; gate means for gating and outputting the output of the frequency dividing means; and counting for one of the two switching signals. reversible counting means that switches the counting direction, and on the other hand switches the down counting direction, and counts the output of the gate means to obtain a digital output of M bits (M is a natural number); and detects the maximum value of the reversible counting means. a first detection means for obtaining a first detection signal by detecting the minimum value of the reversible counting means, a second detection means for obtaining a second detection signal by detecting the minimum value of the reversible counting means, and a multiplication means for multiplying the input digital signal by a coefficient. , an addition or subtraction means for adding or subtracting the output of the reversible counting means and the output of the multiplication means to obtain an output digital signal; The logical product with the detection signal and the logical product with the other of the two switching signals and the second detection signal are taken, and the second
This digital filter is characterized in that the output of the frequency dividing means is gated by the output obtained by calculating the logical sum of two logical product outputs, and a digital proportional-integral circuit can be realized with a relatively simple configuration.

By completely digitalizing the device as described above, external components such as capacitors and resistors can be eliminated, and by incorporating the IC into a built-in circuit, the number of input/output pins can also be reduced.

DESCRIPTION OF THE EMBODIMENTS FIG. 4 shows a first embodiment of the present invention, and FIG. 5 is an operational waveform diagram thereof.

In Figure 4, 5 is N bits (N is a natural number)
reference signal generating means for generating an N-bit reference digital signal as a reference for the input digital signal;
6 is a size discrimination means, 7 is a frequency dividing means, 8 is a gate means, 9 is a reversible counting means (hereinafter referred to as an up-down counter), and 10 is the up-down counter 9.
11 is a second detection means for detecting that the count value of the up-down counter 9 has become equal to or less than a predetermined count value; D ₁ is an N-bit input digital signal, D ₂ is an N-bit reference digital signal generated by the reference signal generation means 5, D ₃ is the output of the uptown counter 9, and S ₁ and S ₂ are the First and second switching signals according to the magnitude relationship between digital signals _D1 and _D2 , _S3 is a clock pulse, _S4 is the output of the frequency dividing means 7, _S5 and _S6 are the outputs of the gate means 8, S ₇ and _S8 are the first and second detection signals.

Input digital signal D ₁ and reference digital signal
_D2 is input to the size determining means 6 to determine the size. Digital signals D ₁ and D ₂ of the size discrimination means 6
first and second switching signals S ₁ representing the magnitude relationship between
_S2 is the input _S5 , _S6 which switches the counting direction of the up-down counter 9 via the gate means 8, and the output _S4 of the frequency dividing means 7 is used as the clock input. ), the frequency dividing means 7 is configured to obtain an output digital signal D ₃ by dividing the input clock pulse S ₃ to obtain a reference digital signal D ₂ and an input digital signal.
A number of pulses proportional to the absolute value of the difference with _D1 are generated and output, and are used as the clock input of the up-down counter 9. Here, the reason why the frequency dividing means 7 creates a number of pulses proportional to the absolute value of the difference between the reference digital signal D ₂ and the input digital signal D ₁ is to convert the output digital signal D ₃ into the input digital signal D _1. This is to make it proportional. This operation corresponds to the fact that the current flowing through the input resistor 2 in the conventional example is proportional to the potential difference between _E1 and _E2 . In addition, in order to prevent overflow and underflow of the up-down counter 9, the first and second detection means 10,
11, the maximum value and minimum value are detected, and the gate means 8 is controlled by the obtained first and second detection signals S ₇ and S ₈ to output the first and second switching signals S ₁ and S _2. The configuration is such that gate outputs S ₅ and S ₆ are obtained by inhibiting the first and second detection signals S ₁ and S ₂ .

As a result, when the count value of the counter 9 reaches the maximum value, the up count is stopped, the state of the counter 9 is maintained, and in preparation for the next operation, that is, the down count, and when the count value reaches the minimum value, the down count is stopped. The counter 9 is stopped, the state of the counter 9 is held, and the counter 9 is prepared for the next operation, that is, up-counting.

To explain the operation of FIG. 4 with reference to FIG. 5, the magnitude determining means 6 determines whether the input digital signal D ₁ and the reference digital signal D ₂ are large or small, and whether the value of D ₁ is larger or smaller than D ₂ . The operation of the up-down counter 9 is switched between up and down (or down and up). If the relationship between D ₁ and D ₂ is D ₁ > D ₂ (or D ₁ < D ₂ ), count up (t ₂ to _{t 3} ), and if D ₁ = D ₂ , stop counting (t ₁ to t ₂ , t _{3 )} ~ _t4 , _t5
~), and if D ₁ < D ₂ (or D ₁ > D ₂ ), the countdown is performed (~t ₁ , t ₄ ~ _{t 5} ). The operation of the output D ₃ of the up-down counter 9 shown in the figure is the same as when D ₁ ≠ D ₂ .
Although a specific case is shown in which the absolute value of the difference between D ₂ and D ₁ is specified, in actual operation, a number of pulses proportional to the absolute value of the difference between D ₂ and D ₁ is inputted from the frequency dividing means 7. Therefore, the slope changes. As a result, the first embodiment of the present invention shown in FIG. 4, which is completely digitalized, makes it possible to realize a digital filter having the function of an integral element. Time constant corresponding to equation (1)
T ₁ is T ₁ = 1/f _CK ... (4) However, f _CK is the lowest frequency of the clock pulse S ₄ which is the output of the frequency dividing means 7 (the absolute value of the difference between D ₂ and D ₁ is 1). ).

FIG. 6 shows a specific circuit example of the up-down counter 9 shown in FIG. 12 is a clock pulse input terminal, 13 is an up signal input terminal, 14 is a down signal input terminal, and 15 to 18 are digital signal output terminals. A composite gate consisting of AND gates 19, 20 and an OR gate 21 and a flip-flop 22 form a unit bit of an up-down counter,
The up-down counter 9 can be constructed by connecting the required number of bits. The saw circuit has input terminal 1
When 3 is "H" and 14 is "L", it operates as an up counter that uses the Q bar output of the front flip-flop as the clock input, and when the input terminal 13 is "L" and 14 is "H", the Q output of the front flip-flop is Operates as a down counter with input.
Further, when both input terminals 13 and 14 are at "L", no clock is input to each flip-flop and the counter stops. Output digital signals can be obtained from output terminals 15-18.

FIG. 7 shows a specific circuit example of the frequency dividing means of FIG. 4, and FIG. 8 is a waveform diagram for explaining its operation.

In FIG. 7, 23 is the input terminal of the clock pulse _S3 , and 24 to 27 are the absolute value of the difference between the input digital signal _D1 and the reference digital signal _D2 | _D1 - _D2
28 is the output terminal of the frequency-divided clock pulse _S4 , 29-32 are flip-flops forming a frequency division counter, 33 is an inverter for inverting the clock pulse, 34-37 are the input terminals of LSB to MSB of |
Absolute value of the difference between D ₁ and D ₂ |D ₁ −D ₂ | and inverter 3
An AND gate 38 inputs and decodes the output of 3 and the outputs of flip-flops 29 to 32.
This is an OR gate that takes the sum of the outputs of AND gates 34-38.

The operation shown in FIG. 7 will be explained with reference to FIG. _S3 is a clock pulse input to frequency division counters 29-32, and _Q1 - _Q4 are Q outputs, respectively. _G1 ～ _G4
is when input terminals 24 to 27 are all “H”
These are the outputs of AND gates 34-37. Now, assuming that the reference digital signal D ₂ is "1000" and the input digital signal D ₁ is "1101" or "0011", the absolute value of the difference between D ₁ and D ₂ |D ₁ −D ₂ | is "0101". ”
Therefore, AND gates 34 and 36 open, and 3
5 and 37 are closed, and the output _S4 of the OR gate 38 can output five clock pulses in one cycle of the frequency division counter. That is, a number of pulses proportional to the absolute value |D ₁ −D ₂ | of the difference between D ₁ and D ₂ can be obtained as the frequency-divided output S ₄ .

Here, the frequency dividing means 7 will be explained more generally.
When the number of bits of the reference digital signal and the input digital signal is N, the number of bits of the frequency division counter needs to be N bits. Then, the clock pulse _S3 and the output of the frequency division counter are decoded (AND
gates 34 to 37), 2 ^A pulses (A = 0, 1, ..., N-1) of N types (G ₁ to G ₄ ) and select the N types of pulses according to the absolute value of the difference (|D ₁ −D ₂ |) (AND gates 34 to 37 and OR gate 38) and output them.
It has _S4 configuration. As a result, the frequency dividing means takes 2 ^N periods of clock pulses as a unit period, and outputs a number of pulses in proportion to the absolute value of the difference between the input digital signal and the reference digital signal for each unit period. be able to.

FIG. 9 shows a second embodiment of the present invention, in which multiplication means 39 and addition means 40 are added to the first embodiment shown in FIG. That is, the output _D4 obtained by multiplying the input digital signal _D1 by the coefficient K in the multiplication means 39 is added to the output _D3 of the up-down counter 9 in the addition means 40, and the obtained output _D5 is used as the output digital signal. It is. This makes it possible to realize a proportional+integral circuit in which a proportional element is added to the integral element of the first embodiment. T ₂ /T ₁ in equation (3) can be obtained as T ₂ /T ₁ =K (5) FIG. 10 is a waveform diagram for explaining the operations of FIGS. 4 and 9. Now, the input digital signal D ₁ is
It has a minimum value at time t ₀ , increases from time t ₁ , becomes equal to the reference digital signal D ₂ at time t ₂ , increases again from time t ₃ , reaches the maximum value at time t ₄ , and increases from time t ₆ . decreases, becomes equal to D ₂ at time t ₇ , decreases again from time t ₈ , reaches a minimum value at time t ₁₀ , increases from time t ₁₂ , becomes equal to D ₂ at time t ₁₃ , but still increases, It becomes a constant value at time t ₁₅ , and the time
It decreases from t ₁₆ , becomes equal to D ₂ at time t ₁₇ , but still decreases, becomes constant at time t ₁₈ , increases from time t ₁₉ , becomes equal to D ₂ at time t ₁₀ , but continues to increase,
An example will be explained in which it becomes a constant value at time t ₂₁ , decreases from time t ₂₂ , becomes equal to D ₂ at time t ₂₃ , still decreases, and becomes a constant value at time t ₂₄ . Further, a case is shown in which the reference digital signal _D2 is the center value of the input digital signal _D1 .

The output _D3 of the up-down counter 9 counts up when the relationship between the input digital signal _D1 and the reference digital signal _D2 is _D1 > _D2 , and _D1 < _D2.
An example of how to count down when
It is configured to stop counting when D ₁ = D ₂ . Note that D ₁ , D ₂ , and D ₃ are each expressed in analog form.

Here, when the input digital signal _D1 undergoes the above-mentioned state change, the output of each means changes as follows. First switching signal S ₁ of the size determining means 6
is "H" during the periods _t3 to _t7 , _t13 to _t17 , and _t20 to _t23 and "L" during the other periods, and the second switching signal _S2 is _{at t0.}
The period from ~ _t2 , _t8 ~ _t13 , _t17 ~ _{t20t23 ~} is "H", and the other periods are "L". On the other hand, the first detection output S7 of the first detection means ₁₀ that detects the maximum value of the output _D3 of the up-down counter 9 is "L" during the period from _t5 to _t9 and "H" during the other periods. The second detection output _S8 of the second detection means 11 that detects the minimum value is
The periods from t ₁₁ to _{t 14} and t ₂₅ are “L” and the other periods are “H”
becomes. However, the output S ₅ of the gate means 8 is t ₃
The period of ~ _t5 , _t13 ~ _t17 , _t20 ~ _t23 is "H" and the other periods are "L", and the output _S6 is _t0 ~ _t2 , _t8 ~ _t11 ,
The period from t ₁₇ to _{t 20} and t ₂₃ to t ₂₅ is “H” and the other period is “L”.

As described above, the up-down counter 9 counts up when the outputs S ₅ and S ₆ of the gate means 8 are "H" and "L", counts down when the outputs S 5 and S 6 of the gate means 8 are "L" and "H", and counts down when the outputs S 5 and S 6 of the gate means 8 are "L". I am trying to stop counting when .

As described above, the switching signals S ₁ and S ₂ are the detection signals S ₇ and S ₈
After gated by, updown counter 9
Since the up-down counter 9 is used as a switching signal to switch the counting direction, when the up-down counter 9 up-counts and reaches the maximum value, it stops counting and prepares for the next down-count, and when it down-counts and reaches the minimum value, it starts counting. It is possible to stop and prepare for the next up count, and prevent overflow and underflow.

Note that by switching the first and second detection outputs S ₇ and S ₈ and also switching the outputs S ₅ and S ₆ , the operation of the up-down counter 9 can be reversed; this is simply a matter of polarity. It is. However, in this case, the addition means 41 must be a subtraction means, and must be configured to subtract D ₄ from D ₃ .

In the second embodiment of the present invention described above, multiplication by a power of 2 by the multiplication means 39 can be handled by simply shifting the bits of the input digital signal _D1 without requiring a particularly complex multiplication circuit. .

Further, in the first and second embodiments, the reference signal generating means 5 does not particularly require a gate circuit or the like, and can simply generate a fixed binary digital signal of "H" or "L". I can do it. Further, up/down commands to the up/down counter 9 are output from the size determining means (switching signals) S ₁ , S ₂
A configuration using either one of these is possible, and the gate means 8 uses the output (switching signal) of the size discrimination means S ₁ , S ₂
It goes without saying that the objective can be achieved in the same way by adopting a configuration in which the output _S4 of the frequency dividing means 7 is gated instead of gated.

Effects of the Invention The digital filter of the present invention includes a reference signal generation means, a magnitude discrimination means, a frequency dividing means, a gate means, a reversible counting means (up-down counter), a first and a second
An integral circuit can be realized with a relatively simple configuration using a detection means, and a proportional + integral circuit can be realized by using a multiplication means and an addition means (or a subtraction means). No peripheral components are required, and it can be used as an IC internal circuit. The number of pins can be eliminated, etc.
Its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one example of a conventional filter, FIG. 2 is an operating waveform diagram thereof, FIG. 3 is a block diagram showing another example of a conventional filter, and FIG. 4 is a block diagram of a digital filter according to the present invention. A block diagram showing the first embodiment, Fig. 5 is its operating waveform diagram, Fig. 6 is a specific circuit diagram of the up-down counter, Fig. 7 is a specific circuit diagram of the frequency dividing means, and Fig. 8 is its operating waveform diagram. , No. 9
The figure is a block diagram of a second embodiment of the digital filter of the present invention, and FIG. 10 is a detailed operational waveform diagram of the first and second embodiments. 5... Reference signal generation means, 6... Size discrimination means, 7... Frequency division means, 9... Reversible counting means (up-down counter), 10... First detection means, 1
1... second detection means, 39... multiplication means, 40...
...addition means (or subtraction means).

Claims (1)

[Claims] 1. Reference signal generating means for generating and outputting a reference digital signal of N bits (N is a natural number); a size determining means for outputting a first switching signal representing "large" and a second switching signal representing "small"; gate means for gating and outputting each of the two switching signals; and ^2N clock pulses. Let the period be a unit period,
frequency dividing means for outputting a number of pulses proportional to the absolute value of the difference between the input digital signal and the reference digital signal for each unit period; and one of the two switching signals via the gate means; reversible counting means that switches a counting direction, and on the other hand switches a down counting direction, and counts the output of the frequency dividing means to obtain an output digital signal of M bits (M is a natural number); a first detection means for detecting a value to obtain a first detection signal and inputting one of the two switching signals to the gate means; detecting a minimum value of the reversible counting means to obtain a second detection signal; A digital filter comprising: second detection means for obtaining a detection signal and inputting the other of the two switching signals to the gate means. 2. a reference signal generating means for generating and outputting an N-bit (N is a natural number) reference digital signal; a magnitude determining means for outputting a switching signal of 1 and a second switching signal representing "small"; a gate means for gating and outputting the ^two switching signals respectively;
frequency dividing means for outputting a number of pulses proportional to the absolute value of the difference between the input digital signal and the reference digital signal for each unit period; and one of the two switching signals via the gate means; reversible counting means that switches the counting direction and on the other hand switches the down counting direction and counts the output of the frequency dividing means to obtain a digital output of M bits (M is a natural number); and a maximum value of the reversible counting means. a first detection means that detects the minimum value of the reversible counting means to obtain a first detection signal and inputs one of the two switching signals to the gate means; and a second detection means that detects the minimum value of the reversible counting means. a second detection means for obtaining a signal and inputting the other of the two switching signals to the gate means; a multiplication means for multiplying the input digital signal by a coefficient; and an output of the reversible counting means and the multiplication means What is claimed is: 1. A digital filter comprising: an addition or subtraction means for adding or subtracting an output and obtaining an output digital signal.