JPH0465569B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital integration circuit that obtains a binary output digital signal by adding integral characteristics to a binary input digital signal.

Conventional configurations and their problems Recently, the digitalization of home VTRs, especially the servo system, has been active, and digital servo systems have already been developed.
It has been commercialized and introduced as an IC (integrated circuit). The aim of this digitalization is to reduce the number of adjustment parts and peripheral parts, reduce power consumption, improve reliability, and support multi-functionality, and a considerable amount of digitalization is being achieved. However, only the phase compensation circuit (hereinafter referred to as a filter) that determines the servo characteristics of a rotary servo system, etc., is still composed of a resistor and a large electrolytic capacitor.

As a conventional example of such a filter, there is an analog integration circuit shown in FIG. Further, FIG. 2 is a waveform diagram for explaining the operation.

The components of the analog integrating circuit are an operational amplifier 1, an input resistor 2, and a feedback capacitor 3. now,
When a potential difference occurs between input voltages E ₁ and E ₂ , input resistance 2
A current flows, the feedback capacitor 3 is charged, and the output voltage E ₀ changes. As shown in Fig. 2, the potential of the output voltage _E0 decreases (~ _t1 , _t4 ~t5) when _E1 > _E2 , and stops (~ _t1 ~ _t5 ) when _E1 = _E2 . _t2 , _t3 to _t4 , _t5
), and when E ₁ < E ₂ , the potential increases (t ₂ to _{t 3} ). The transfer function G(s) of this circuit is G(s)=1/sT (1). However, T ₁ =C ₁ ·R ₁ , C ₁ is the capacitance of the feedback capacitor 3, and R ₁ is the resistance value of the input resistor 2.
In other words, this circuit functions as an integral element.

Note that since the magnitude of the current flowing through the input resistor 2 is proportional to the potential difference between the input voltages E ₁ and E ₂ , charging and discharging of the charge in the feedback capacitor 3 is also proportional. However, the slope of the output voltage E ₀ shown in FIG. 2 is E ₁ , E ₂
It changes in proportion to the potential difference between.

The analog integrating circuit shown in Fig. 1 explained above is
The input voltage E ₁ is an input analog signal, the input voltage E ₂ is a reference analog signal, and the output voltage E ₀ is an output analog signal, and the output analog signal is a signal obtained by adding integral characteristics to the input analog signal.

When converting such an integrating circuit into an IC, three pins for input/output and an external CR component are required, which hinders the reduction of external components and the number of pins when converting into an IC. In addition, it was susceptible to variations in CR components, changes in power supply voltage, changes in temperature, changes over time, etc. Furthermore, if you want to switch the frequency characteristics to many types using the mode command signal,
There were problems such as the need for more external parts.

Purpose of the Invention The present invention solves the above-mentioned conventional problems.
The object of the present invention is to provide a digital integration circuit in which all the components are digitalized and whose characteristics can be switched by a mode command signal.

Structure of the Invention The present invention comprises variable frequency dividing means for changing the frequency division ratio of a clock pulse in accordance with a mode command signal, and blocking the output of the variable frequency dividing means when a binary input digital signal is a predetermined value. a gate means for passing the digital signal when the value is other than a predetermined value; and a gate means for inputting at least one most significant bit of the input digital signal as a counting direction switching signal to switch the up/down counting direction, and controlling the output of the gate means for clock pulses. a reversible counting means for inputting and counting as
A digital integrating circuit which obtains an output digital signal corresponding to the mode command signal from the reversible counting means; a circumferential means, and 2
a second frequency dividing means for dividing the output of the first frequency dividing means into a frequency proportional to the absolute value of the difference between the base input digital signal and a predetermined value; and at least one most significant bit of the input digital signal. reversible counting means inputted as a counting direction switching signal to switch the up/down counting direction, and counting by inputting the output of the gate means as a clock pulse, the reversible counting means receiving the mode command signal; This is a digital integration circuit that obtains an output digital signal corresponding to .

By completely digitizing the device as described above, external components such as capacitors and resistors are no longer required, and the number of input/output pins can also be reduced by incorporating the IC into a built-in circuit.

DESCRIPTION OF THE EMBODIMENTS FIG. 3 is a block diagram showing a first embodiment of the present invention, FIG. 4 is its operating waveform diagram, and FIG. 5 is a frequency characteristic curve showing the integral characteristic.

In FIG. 3, 4 is a variable frequency dividing means, 5 is a gate means, 6 is a reversible counting means (hereinafter referred to as an up-down counter), _D1 is a binary input digital signal, and _D2 is a binary input digital signal. The output digital signal is _S1 is the clock pulse, _S2 is the divided output, and _S3 is the gate output.

The clock pulse S ₁ is frequency-divided by the variable frequency dividing means 4 at a predetermined frequency dividing ratio according to the mode command signal, and the frequency divided output S ₂ is inputted to the gate means 5 . In the gate means 5, the input digital signal D ₁
When matches the predetermined value D ₀ (D ₁ = D ₀ ), the passage of the divided output S ₂ is blocked, and when they do not match (D ₁ ≠ D ₀ ), the divided output S ₂ is passed and the gate output _S3 and input as the clock pulse of the up-down counter 6. On the other hand, at least one most significant bit of the input digital signal _D1 is input to the up-down counter 6 as a counting direction switching signal, and the gate output _S3 is counted. For example, the up-down counter 6 counts the gate output _S3 , which is a clock pulse, so that it counts up when the counting direction switching signal is "1" and counts down when it is "0".
The configuration is such that an output digital signal _D2 is obtained from the up-down counter 6.

To explain the operation of FIG. 3 in more detail with reference to FIG. 4, the operation of the up-down counter 6 is controlled to be up or down (or down or up) depending on whether the input digital signal _D1 is larger or smaller than the predetermined value _D0 . ). That is, the output digital signal
D ₂ counts up (t ₂ to _{t 3} ) when D ₁ > D ₀ (or D ₁ < D ₀ ), and stops counting (t ₁ to _{t 2} , t ₃ to _{t 4} ) when D ₁ = D ₀ . ，
t ₅ ~), and when D ₁ <D ₀ (or D ₁ >D ₀ ), the countdown is performed (~t ₁ , t ₄ ~ _{t 5} ).

Here, to detect whether D ₁ >D ₀ or D ₁ <D ₀ , it is sufficient to use at least one most significant bit of the input digital signal D ₁ . For example, the input digital signal
As an example, assume that D ₁ is 6 bits and the predetermined value D ₀ is "100000" (this is the case where the most significant bit is "1" and all other lower bits are "0").
When the most significant bit of D ₁ is "1", D ₁ > D ₀ ,
If D ₁ <D ₀ when the value is "0", it is possible to easily detect whether the value is large or small. In this case, similar detection is possible even if the predetermined value D ₀ is set to "011111".

In the above example, input digital signal with predetermined value D ₀
When setting the value to 1/2 of D ₁ , 1/4, 3/4
It is also possible to set the value to , in which case the most significant two bits may be used and a logic circuit (decoder) may be used for detection.

On the other hand, in the gate means 5, the input digital signal
D ₁ is decoded, and when D ₁ =D _0, an inhibition signal is obtained to prevent the frequency-divided output S ₂ from passing.

Here, the time constant T in equation (1) can be obtained as T=1/fck (2). However, fck is the frequency of the clock pulse input to the up-down counter 6. This clock frequency fck is the frequency of the divided output S ₂ obtained by dividing the clock pulse S ₁ by the variable frequency dividing means 4 according to the mode command signal, and the frequencies are 2πf ₁ , 2πf ₂ , 2πf ₃ , . . . By dividing the frequency so that

FIG. 6 is a block diagram showing a second embodiment of the invention.

In FIG. 6, 7 is the first frequency dividing means, and 8 is the second frequency dividing means.
The frequency dividing means 9 is an up-down counter;
D ₀ is a predetermined value, D ₁ is an input digital signal, D ₂ is an output digital signal, S ₄ is a clock pulse, S ₅ is a first frequency division output, and S ₆ is a second frequency division output.

The first frequency dividing means 7 corresponds to the variable frequency dividing means 4 shown in FIG. 3, receives the clock pulse _S4 and the mode command signal, and serves for switching the frequency characteristics as described above. The second frequency dividing means 8 is the first frequency dividing means 7
receives the divided output _S5 , divides the first divided output _S5 into a frequency proportional to the absolute value of the difference between the input digital signal _D1 and the predetermined value _D0 , and outputs the second divided output. S ₆
is input as a clock pulse to the up-down counter 9. The output digital signal D ₂ can be obtained as the output of the up-down counter 9.

This allows input digital signal D ₁ and predetermined value
Up-counting and down-counting are possible in proportion to the absolute value of the difference from D ₀ |D ₁ −D ₀ |. This digitally realizes charging and discharging proportional to the input of the feedback capacitor 3 shown in the conventional example shown in FIG.

Here, the clock frequency fck in equation (2) is the lowest frequency of the second divided output S ₆ , that is, when the absolute values of D ₁ and D ₀ are “1” (|D ₁ − D ₀ |=1). This is the frequency of the time.

Furthermore, the up-down counters 6 and 9 of the first and second embodiments are provided with an output digital signal to prevent overflow and underflow.
By decoding D ₂ , the clock pulse that is input when D ₂ is the maximum value and minimum value is prohibited, and when the maximum value is detected, a down command of the counting direction switching signal is issued, and when the minimum value is detected, an up command is issued. What is necessary is to add a function to cancel the prohibition.

Incidentally, if a plurality of required clock pulses are prepared, a selection means may be used in place of the variable frequency dividing means 4 and the first frequency dividing means 7, and selection may be made by the mode command signal.

Effects of the Invention As described above, the present invention has a relatively simple configuration that only uses a variable frequency dividing means, a gate means, and a reversible counting means (up-down counter), or
An integrating circuit can be realized with a relatively simple configuration using only a first frequency dividing means, a second frequency dividing means, and a reversible counting means (up-down counter), and the frequency characteristics of the integrating circuit can be switched according to a mode command signal. I can do it.

Furthermore, all components can be digitalized, eliminating the need for external components, and by incorporating built-in circuits, input/output pins can be eliminated.
It is extremely useful for

[Brief explanation of the drawing]

Figure 1 is an electrical wiring diagram showing the configuration of a conventional analog integration circuit, Figure 2 is its operating waveform diagram, and Figure 3 is an electrical connection diagram showing the configuration of a conventional analog integration circuit.
The figure is a block diagram of the digital integration circuit in the first embodiment of the present invention, and FIG. 4 is its operating waveform diagram.
FIG. 5 is a frequency characteristic curve diagram thereof, and FIG. 6 is a block diagram of a digital integration circuit in a second embodiment of the present invention. 4... variable frequency dividing means, 5... gate means, 6,
9... Reversible counting means, 7... First frequency dividing means, 8...
...Second frequency dividing means.

Claims (1)

[Scope of Claims] 1. Variable frequency dividing means for changing the frequency division ratio of a clock pulse in accordance with a mode switching signal; and blocking the output of the variable frequency dividing means when a binary input digital signal is a predetermined value; gate means for passing the digital signal when the value is not a predetermined value; and inputting at least one most significant bit of the input digital signal as a counting direction switching signal to switch the up/down counting direction, and controlling the output of the gate means as a clock pulse. a reversible counting means for inputting and counting as an input signal, and obtaining an output digital signal corresponding to the mode command signal from the reversible counting means. 2. A first frequency dividing means that changes the frequency division ratio of the clock pulse in accordance with the mode switching signal; and an output of the first frequency dividing means that changes the frequency proportional to the absolute value of the difference between the binary input digital signal and a predetermined value. a second frequency dividing means for dividing the frequency of the second frequency dividing means; and a second frequency dividing means for inputting at least one most significant bit of the input digital signal as a counting direction switching signal to switch the up/down counting direction; a reversible counting means for inputting and counting a clock pulse as a clock pulse, and obtaining an output digital signal corresponding to the mode command signal from the reversible counting means.