JPH0446005B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital filter that obtains a binary output digital signal by adding frequency characteristics to a binary input digital signal.

Configuration of a conventional example and its problems FIG. 1 is a conventional example of an analog type integrating circuit, and FIG. 2 is a waveform diagram for explaining its operation.

The components of the analog integrated layer circuit are an operational amplifier 1, an input resistor 2, and a feedback capacitor 3. When a potential difference occurs between the input voltages E ₁ and E ₂ , a current flows through the input resistor 2 , a charge flows through the capacitor 3 , and the output voltage E ₀ changes. When E ₁ > E ₂ , the potential of the output voltage E ₀ drops (~t ₁ , t ₄ ~ _{t 5} ), and when E ₁ = E ₂ , the potential stops (t ₁ ~ t ₂ , t ₅ ~). , when E ₁ <E _{2 ,} the potential increases (t ₂ to _{t 3} ). The transfer function G(s) of this circuit is G(s)=1/ST ₁ (1) However, T ₁ = C ₁ R ₁ , the capacitance of C ₁ feedback capacitor 3,
R ₁ is the resistance value of the input resistor 2. That is, it functions as an integral element.

In addition, in the specific circuit example shown in Figure 1, the input voltage
E ₁ is the input analog signal, input voltage E ₂ is the reference analog signal, output voltage E ₀ is the output analog signal,
The output analog signal is a signal obtained by adding integral characteristics to the input analog signal.

When converting this integration circuit into an integrated circuit (IC), three pins for input/output and two external CR components are required, which hinders the reduction of external components and the number of pins by converting into an IC. was.

Purpose of the Invention The present invention solves the above-mentioned conventional problems.
The object of the present invention is to provide a digital filter in which all components are digitized.

Structure of the Invention The present invention includes a reference signal generating means for generating a reference digital signal having a reference value D ₂ (fixed value), and an input value D 2 (fixed value).
An input digital signal of _D1 (variable value) and the reference digital signal are input, the input value _D1 is compared with the reference value _D2 , and when _D1 > _D2 , the first switching signal is set to D. ₁ <D ₂ , a size determining means for outputting a second switching signal;
a gate means for gating and outputting a switching signal, and a first switching signal passing through the gate means to increase or decrease the counting direction, and a second switching signal passing through the gate means to increase or decrease the counting direction. is set to down (or up) and a clock pulse is input to the first stage, and when the counting direction is set to up, the clock pulse counts up, and when the counting direction is set to down, the clock pulse is input. Count down with
When the counting direction is not set to either up or down (when D ₁ = D ₂ ), the up-down counter stops counting by the clock pulse, and the maximum value of the up-down counter is detected, and the gate means a first gate for gating the first switching signal (or the second switching signal);
and a second detection signal for detecting the minimum value of the up-down counter and gating the second switching signal (or the first switching signal) in the gate means, This is a digital filter that obtains an output digital signal from a counter, and can realize a digital integration circuit with a relatively simple configuration.

By completely digitalizing the device as described above, external components such as capacitors and resistors can be eliminated, and by incorporating the IC into a built-in circuit, the number of input/output pins can also be reduced.

DESCRIPTION OF EMBODIMENTS FIG. 3 shows a first embodiment of the present invention, and FIG. 4 is an operating waveform diagram thereof.

In FIG. 3, 4 is a reference signal generation means, 5 is a magnitude discrimination means, 6 is a gate means, 7 is a reversible counting means (hereinafter referred to as an up-down counter), 8 is a first detection means, and 9 is a second detection means. _D1 is a binary input digital signal, _D2 is a binary reference digital signal generated by the reference signal generating means 4, _D3 is a binary output digital signal which is the output of the up-down counter 7, and S ₁ , S ₂ is a means of size 5
The outputs are the first and second switching signals, _S3 is the clock pulse, _S4 and _S5 are the outputs of the gate means ₆ , and S6 and _S7 are the outputs of the first and second detection means 8 and 9, that is, the first , the second detection signal. The binary input digital signal D ₁ and the reference digital signal D ₂ are input to the size determining means 5 to perform size determination. Size discrimination means 5
The first and second switching signals S ₁ and S ₂ indicate whether the
is input to the up-down counter 7 together with the clock pulse S ₃ via the gate means 6. In order to prevent overflow and underflow of the up-down counter 7, the first detection means 8 and the second detection means 9 detect the maximum value and the minimum value. 1. The first and second switching signals are activated by the second detection signals S ₆ and S ₇
The configuration is such that the gate means 6 is controlled so as to inhibit the gate outputs S ₄ and S ₅ of S 1 _and S ₂ .

To explain the operation of FIG. 3 with reference to FIG. 4, the size determining means 5 determines whether the input digital signal D ₁ and the reference digital signal D ₂ are large or small, depending on whether the value of D1 is larger or smaller than D ₂ . The operation of the up-down counter 7 is switched between up and down (or down and up). That is, if the relationship between D ₁ and D ₂ is D ₁ > D ₂ (or D ₁ < D ₂ ), the count is up (t ₂ to t ₃ , t ₆ to _{t 7} ), and if D ₁ = D ₂ , the count is stopped ( t ₁ ~ t ₂ , t ₃ ~ _{t 4} ), and if D ₁ < ₂ (or D ₁ > D ₂ ), it is configured to count down (~ t ₁ , t ₄ ~ t ₅ , t ₈ ~), and When the count value of the counter 7 reaches the maximum value (t ₇ - _{t 8} ), the up-count is stopped, the counter 7 is maintained, and is prepared for the next operation, that is, the down-count, and when the count value reaches the minimum value ( _t5 to _t6 ) Down counting is stopped, the state of the counter 7 is maintained, and the counter 7 is configured to prepare for the next operation, that is, up counting.
This makes it possible to add the function of an integral element. The time constant T ₁ in equation (1) is: T ₁ =1/f _CK (2) However, F _CK can be determined as the frequency of the clock pulse S ₃ .

FIG. 5 shows a specific circuit example of the up-down counter 7 shown in FIG. 10 is a clock pulse input terminal, 11 is an up switching signal input terminal, 12 is a down switching signal input terminal, and 13 to 16 are digital signal output terminals. AND gates 17, 18 and
The composite gate consisting of the OR gate 19 and the flip-flop 20 form a unit bit of an up-down counter, and the up-down counter 7 can be constructed by connecting the required number of bits.

FIG. 6 is a waveform diagram for explaining the operation of FIG. 3. Now, the input digital signal D ₁ has the minimum value at time t ₀ , increases from time t ₁ , becomes equal to the reference digital signal D ₂ at time t ₂ , increases again from time t ₃ , and reaches the maximum value at time t ₄ . value, decreases from time t ₆ , becomes equal to D ₂ at time t ₇ , decreases again from time t ₈ , reaches a minimum value at time t ₁₀ , increases from time t ₁₂ ,
At time t ₁₃ it becomes equal to D ₂ but still increases and at time t ₁₅
It becomes a constant value at time t ₁₆ , decreases from time t 16, and at time t ₁₇
Even though it becomes equal to D ₂ , it still decreases, becomes a constant value at time t ₁₈ , increases from time t ₁₉ , becomes equal to D ₂ at time t ₂₀ , but still increases, and becomes a constant value at time t ₂₁ ,
An example will be explained in which the value decreases from time t ₂₂ , becomes equal to D ₂ at time t ₂₃ , but still decreases, and reaches a constant value at time t ₂₄ . Further, a case is shown in which the reference digital signal _D2 is the center value of the input digital signal _D1 .

The output digital signal D ₃ has a relationship between the input digital signal D ₁ and the reference digital signal D ₂ such that D ₁ >
This shows an example of an operation in which up-counting occurs when D ₂ and down-counting when D ₁ > D ₂ , and the count is stopped when D ₁ = D ₂ . In addition,
D ₁ , D ₂ , and D ₃ are each displayed in analog form.

Here, when the input digital signal _D1 undergoes the above-mentioned state change, the output of each means changes as follows. First switching signal S ₁ of the size determining means 5
is "H" during the periods _t3 to _t7 , _t13 to _t17 , and _t20 to _t23 and "L" during the other periods, and the second switching signal _S2 is _{at t0.}
The period from ~ _t2 , _t8 ~ _t13 , _t17 ~ _t20 , _t23 ~ is "H", and the other periods are "L". On the other hand, the output S 6 (first detection signal) of the first detection means 8 which detects the maximum value of the output digital signal D ₃ of the up-down counter ₇
is "L" during the period _t5 to _t9 and "H" during the other periods, and the output _S7 of the second detection means 9 detects the minimum value.
(Second detection signal) is "L" during the period from _t11 to _t14 , _{t25, . .} . and "H" during the other periods. However, the output _S4 of the gate means 6 becomes an output gated by the first switching signal S1 _and the first detection signal S6, and from _t3 to
The periods t ₅ , t ₁₃ to t ₁₇ , t ₂₀ to _{t 23} are “H” and the other periods are “L”, and the output S ₅ of the gate means 6 and the second switching signal S ₂ are the second detection signal. The output is gated by _S7 , and is "H" during the periods t0 to _t2 , _t8 to _t11 , _t17 to _t20 , and _t23 to _t25 , and "L" _during the other periods.

As described above, the up-down counter 7 switches the up/down counting direction using the outputs S ₄ and S ₅ of the gate means 6, and by counting the clock pulse S ₃ , the outputs S ₄ and S ₅ of the gate means 6 are changed. When “H” and “L”, count up, “L”,
When both are "H", the count is down, and when both are "L", the count is stopped.

As described above, the switching signals S ₁ and S ₂ are the detection signals S ₆ and S ₇
This is used as a switching signal to switch the counting direction of the up-down counter 7, so when the up-down counter 7 counts up and reaches the maximum value, it stops counting and prepares for the next down count. When the count reaches the minimum value, the count can be stopped to prepare for the next up count, and overflow and underflow can be prevented.

Note that when outputs S ₆ and S ₇ are swapped, outputs S ₄ and S ₅
By replacing the numbers, the operation of the up-down counter 7 can be reversed. This is ultimately a matter of polarity, and either can be adopted. Further, the reference signal generating means 4 does not particularly require a gate circuit or the like, and can simply generate a fixed binary digital signal indicating whether "H" or "L".

Effects of the Invention The digital filter of the present invention is simple and includes a reference signal generation means 4, a magnitude discrimination means 5, a gate means 6, a reversible counting means (up-down counter) 7, and first and second detection means 8, 9. Depending on the configuration,
A digital filter with the function of an integral element can be provided, and an up-down counter 7 can also be provided.
The clock pulse _S3 is always inputted to the first stage of the counter, and the size determining means 5 is configured to stop counting in the up-down counter 7 only when _D1 = _D2 , so that the clock pulse S3 is continuously inputted in synchronization with the clock pulse _S3 . The counting output (integral output D _{3 )} is obtained from the up-down counter 7. Furthermore, the up-down counter 7 stops counting only at one point D ₁ = D ₂ and there is no "dead zone", so the operation of the analog integration circuit is can be realized as is with a digital circuit.It has great practical effects, such as not only eliminating the need for external components when converting it into an IC, but also eliminating the need for input/output pins by making it a built-in circuit of the IC.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the conventional configuration of an integrating circuit, FIG. 2 is its operating waveform diagram, FIG. 3 is a block diagram of a digital filter according to an embodiment of the present invention, and FIG. 4 is its operating waveform diagram. FIG. 5 is a specific circuit diagram of the up-down counter, and FIG. 6 is an operational waveform diagram of FIG. 3. 4... Reference signal generation means, 5... Size discrimination means, 6... Gate means, 7... Reversible counting means (up-down counter), 8... First detection means,
9...Second detection means.

Claims (1)

[Claims] 1. A reference signal generating means for generating a reference digital signal having a reference value D ₂ (fixed value); an input digital signal having an input value D ₁ (variable value) and the reference digital signal; Said input value
D ₁ is compared with the reference value D ₂ and when D ₁ > D ₂ , the first
a gate means for gating and outputting the _first switching signal and the _second switching signal, respectively; A first switching signal passed through the gate means sets the counting direction up (or down), a second switching signal passed through the gate means sets the counting direction down (or up), and the clock pulse is set to the first stage. When the counting direction is set to up, the clock pulse counts up; when the counting direction is set to down, the clock pulse counts down; and when the counting direction is set to up or down, the clock pulse counts down. an up-down counter that stops counting by the clock pulse when not set (when D ₁ = D ₂ ); and detecting the maximum value of the up-down counter;
a first detection means for gating the first switching signal (or the second switching signal) in the gate means; detecting a minimum value of the up-down counter;
a second detection means for gating the second switching signal (or the first switching signal) in the gate means, and configured to obtain an output digital signal from the up-down counter.