JPS5977716A - Digital filter - Google Patents

Abstract

PURPOSE:To realize the function of integrating element by discriminating whether or not an input signal is larger than a reference value and counting the result. CONSTITUTION:A binary input signal D1 and a binary reference signal D2 are inputted to a level discriminating circuit 5, and when D1>D2, count-up is commanded to a counter 7 of the next stage. When D2>D1, down-count is commanded to the counter 7 of the next stage. The command of up/down count is performed via a gate means 6 located at the pre-stage of the counter 7. When the command is inquired, the gate means 6 passes a clock pulse. When the counter 7 counts a maximum or a minimum value, the count is stopped unit the relation between the D1 and D2 is changed. The function of integrating element is realized with the simple constitution in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital filter that obtains an output with frequency characteristics added to a binary digital signal input.

Structure of a conventional example and its problems FIG. 1 shows a conventional example of an analog type integrating circuit, and FIG. 2 is a waveform diagram for explaining its operation.

The components of the analog integration circuit are an operational amplifier 1, an input resistor 2, and a return capacitor 3. Input voltage & , 12
When a potential difference occurs between the two, a current flows through the input resistor 2, charging the capacitor 3 and increasing the output voltage g.

changes. Output voltage Eo is 1>1! : When 2, the potential decreases (~t+, t4~
t5) When E1 = Equation, the potential stops (11 to t2.
t5~), and the potential rises when E+ (Ez) (t2~t
s). The transfer function G (
s), where T1 = C+ R+, G1 is the capacitance of the return capacitor 3, and R1 is the resistance value of the input resistor 2. That is, it has a function as an integral element.

When converting this integration circuit into an integrated circuit (IC), three input/output pins and two external OR components are required.
External attachment due to IC has been an impediment to reducing the number of parts and the number of pins.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional problems, and aims to provide a digital filter in which all the constituent elements are digitalized.

Structure of the Invention The present invention includes a reference signal generation means for generating a binary digital signal as a reference, a magnitude determination between the output of the reference signal generation means and a binary input digital signal, and a 1. A magnitude determining means for outputting a second signal, a gate means for gating and outputting the first and second signals, and an up/down counter receiving the output of the gate means and a clock pulse as input; A digital filter comprising first and second detection means for detecting the maximum value and minimum value of the up-counter and controlling the gate means, and obtaining a binary digital signal output from the up-down counter, By completely digitizing the system, external parts can be completely eliminated, and by incorporating the IC into a built-in circuit, the number of input/output pins can also be reduced.

DESCRIPTION OF THE EMBODIMENTS FIG. 3 shows a first embodiment of the present invention, and FIG. 6 is an operational waveform diagram thereof.

In FIG. 3, 4 is a reference signal generation means, 5 is a magnitude discrimination means, 6 is a gate means, 7 is an up/down counter, and 8
9 is a first detection means, 9 is a second detection means, Dl is a binary digital signal input, D2 is a reference digital signal generated by the reference signal generating means 4, and D5 is an output of the up/down counter 7, which is a binary number. Digital signal output, 81
, S2 is the output of the size discriminating means 5 and the first . second signal,
S3 is a clock pulse, 84, ss is gate means 6
The outputs S6 and S7 are the outputs of the first and second detection means 8 and 9. A binary digital signal input D1 and a reference digital signal D2 are input to a size determining means 60 to perform size determination. The first digit indicates large or small of the size determining means 5.
The second signal s, l S2 is input to the up/down counter 7 via the clock 1 means 6 together with the clock pulse S3.

In order to prevent the up/down counter 7 from overflowing or under 70, the first detection means 8 and the second detection means 9 detect the maximum value and the minimum value. The configuration is such that the gate means 6 is controlled by the outputs of the second detection means 8 and 9 so as to inhibit the gate output 84 #S5 of the first and second signals.

To explain the operation of FIG. 3 with reference to FIG. 4, when the magnitude determining means 5 determines the magnitude of the digital signal input D1 and the reference digital signal D2, an up/down counter is activated depending on whether the value of Dl is larger or smaller than D2. The operation of γ is switched to amplifier or down (or down or up). That is, D
The relationship between l and D2 is Ih>D2 (or, (D2)
Then count up (t2-t3, t6-t7).

I), : If D2, stop counting (11~t2.t3~t
4).

If Dl〈D2 (or)D2), count down (
~t1. t4-t5. t8~), and when the count value of the counter reaches the maximum value (ty~t8), the up count is stopped, and when the count value reaches the minimum value (t5~t6), the down count is stopped. . This makes it possible to add the function of an integral element. The time constant T1 in equation (1) is: T, = -(2) 2πfayc However, fax can be determined as the frequency of the clock pulse S5.

FIG. 5 shows a specific circuit example of the up/down counter 7 shown in FIG. 10 is a clock pulse input terminal, 11 is an up signal input terminal, 12 is a down signal input terminal, 13 to 16
is a digital signal output terminal. AND gate 17.
The unit bit of the up/down counter is formed by a composite gate consisting of 18 and OR gate 19 and the flip-flop 2o, and the up counter 7 can be constructed by connecting the unit bits of the required number of pins.

FIG. 6 is a waveform diagram for explaining the operation of FIG. 3. now,
Digital signal input D1 has a minimum value at time t1, increases from time t1, becomes equal to reference digital signal D2 at time t2, increases again from time t3, and increases from time t1.
It reaches the maximum value at 4, decreases from time t6, and reaches D at time t7.
2, decreases again from time t8, and reaches time too
becomes the minimum value, and the time also increases from 2, and at time t15 D
2, it still increases, becomes a constant value at time t's, decreases from time t16, becomes equal to D2 at time t17, still decreases, becomes a constant value at time t18, increases from time t19, and It becomes equal to D2 at t20, but still increases, becomes a constant value at time t21, decreases from time t22, becomes equal to D2 at time t25, but still decreases,
The case where the value becomes constant at time t24 will be explained as an example. Still, a case is shown in which the reference digital signal D2 is the center value of the digital signal input D1.

The digital signal output D5 shows an operation example in which the amplifier counts when the relationship between the digital signal input D1 and the reference digital signal D2 is Dl)D2, and counts down when the relationship is D+(D2), and counts when the relationship between the digital signal input D1 and the reference digital signal D2 is Dl-D2. It is configured to stop. Note that I>, D2 and D3 are each shown in analog form.

Here, when the digital signal input D1 undergoes the above-mentioned state change, the output of each means changes as follows. The first signal S1 of the size determining means 6 is output from t5 to t7. t+x
~t+7. The period from tzo to t23 is “Hi+” and the other periods are “I” and “II”, and the second signal S2 is from tO to t2.
．． t8~t+5. The period from t+z to t2o and tz5 is "lH11" and the other period is "Lti".On the other hand,
The output S6 of the first detection means 8 which detects the maximum value of the digital signal output D5 of the up/down counter 7 is from t5 to t.
9 is 'L' and the other periods are 'H11', and the output S7 of the second detection means 9 which detects the minimum value is ti1 to t1.
4, the period from t25 is "l, 11 and the other periods are I
IH11. However, the output S4 of the gate means 6 is t! r-15, t13-t17. The period from t20 to t25° is "H..." and the other periods are 17 and 11, and the output S5
are tO~t2 t t8~t++ , t1y~t2
Q, the period from t25 to t25 is H and the other periods are L”
becomes.

As described above, the up/down counter 7 is controlled by the gate means 6.
This is done when the output S4p35 is "H" and "'L°".

Note that while outputs Sb and 37 are replaced, outputs S4.
By replacing Ss, the operation of the up/down counter 7 can be reversed. This is simply a matter of polarity;
Either can be adopted. Further, the reference signal generating means 4 does not particularly require a gate circuit or the like, and can simply generate a fixed binary digital signal of "H" or "L".

Effects of the Invention The digital filter of the present invention includes a reference signal generation means 4, a magnitude determination means 5, a gate means 6, and an up/down counter 7.
, 1st. With a simple configuration that only requires the second detection means 8 and 9, it is possible to provide a digital filter with the function of an integral element, which eliminates the need for external components when integrated into an IC, and also allows integration with the built-in circuit of the IC. This has great practical effects, such as eliminating the need for input/output bins.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the conventional configuration of an integrating circuit, FIG. 2 is its operating waveform diagram, FIG. 3 is a block diagram of a digital filter according to an embodiment of the present invention, and FIG. 4 is its operating waveform diagram.
FIG. 5 is a specific circuit diagram of the up/down counter, and FIG. 6 is an operational waveform diagram of FIG. 3. 4... Reference signal generation means, 5... Size discrimination means, 6... Gate means, 7...
Up/down counter, 8...first detection means, 9...second detection means. Name of agent: Patent attorney Toshio Nakao and 1 other person
1 Figure 2 Figure 3 Figure 5

Claims (1)

[Claims] A reference signal generating means generates a binary digital signal serving as a reference, and the output of the reference signal generating means and the binary digital signal input are determined in magnitude, and the first . a size determining means for outputting a second signal;
．． a gate means for gating and outputting a second signal; an up-down counter receiving the output of the gate means and a clock pulse as input; detecting the maximum value and minimum value of the up-down counter; The first thing to control.
a second detection means, and obtains a binary digital signal output from the up/down counter.