KR950003438Y1 - Digital signal processing apparatus - Google Patents

Abstract

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Description

Digital signal processing device of video equipment

1 is a block diagram showing a conventional digital signal processing apparatus.

2 is a block diagram illustrating a process of converting a 6-bit digital signal into a 4-bit digital signal in the digital signal processing apparatus of the present invention.

3 is a block diagram showing the operation of the digital signal processing apparatus of the present invention.

4 is a detailed circuit diagram showing an embodiment of a digital signal processing apparatus of the present invention.

5 is an operational waveform diagram of each part of FIG.

FIG. 6 is an explanatory diagram showing a state in which a 6-bit digital signal is converted into a 4-bit and 2-bit digital signal and outputted in the digital signal processing apparatus of the present invention.

* Explanation of symbols for main parts of the drawings

100: analogue / digital converter 110: counter

120: digital signal separation output unit 130: trigger signal generator

140,150: monomulti vibrator 160: control signal output unit

170 to 200: 1 to 4 bit signal output unit F ₁ to F ₁₂ : flip-flop

Q ₁ / Q: Output terminal ID ₁ ~ ID ₄ : 1 ~ 4 bit signal

CLK: Clock signal b ₀ ~ b ₅ : Digital signal

The present invention relates to a digital signal processing apparatus of a video device that converts a digital signal of a video signal to a memory in a video device such as a video cassette recorder and a television receiver. The present invention relates to a digital signal processing apparatus for a video device that converts a bit into a digital signal so that the digital signal can be stored in every bit without the remaining bits in the 4-bit and 8-bit memories.

In general, digital video apparatuses, such as a video cassette recorder and a television receiver, convert an analog video signal into a 6-bit digital signal, and store and output the same in a memory.

In general, a memory that is widely used and used is one word (8 bits) or 4 bits. Therefore, a 6-bit digital video signal must be converted into a bit of the memory to be stored and output.

However, in the related art, the 6-bit digital signal output from the analog-to-digital converter is not converted to the bit of the memory appropriately, and is directly applied to the memory and stored, thereby not using the memory efficiently.

That is, conventionally, as shown in FIG. 1, a video signal is converted into a 6-bit digital signal b ₀ to b ₅ by the analog / digital converter 1, and output, and output by the analog / digital converter 1. The 6-bit digital signals b ₀ to b ₅ are directly connected to the input terminals I ₀ to I ₅ (I ₀ to I ₃ ) (I ₀ and I ₁ ) of the memory 2, 2A and 2B. Input was saved.

Therefore, as shown in FIG. 1, when the memory 2 having one word is 8 bits, the 6-bit digital signals b ₀ to b ₅ outputted from the analog / digital converter 1 are inputted to the memory 2. Input and store only at terminals I ₀ ~ I ₅ , and the other input terminals I ₆ , I ₇ do not use because there is no input and stored signal, and as shown in FIG. When two memories 2A and 2B are used, 6-bit digital signals b ₀ to b ₅ output from the analog / digital converter 1 to the input terminals I ₀ to I ₃ of one memory 2A. 4 bits of the digital signal (b ₀ ~ b ₃ ) can be used to input and store all the bits, but the other memory (2B) is the analogue / digital converter only on the input terminals (I ₀ ~, I ₁ ) 1) digital signals (b _4, b ₅₎ are inputted and outputted from the storage, and the other input terminal (2), (2A, 2B), the use efficiency is low there is the problem of The.

The present invention has been made to solve the above-mentioned conventional problems. By converting a 6-bit digital signal into 4 bits and 2 bits and outputting the same, all bits are stored without any unused bits of 4 and 8 bit memories. It is an object of the present invention to provide a digital signal processing apparatus of a video device having a simple configuration for storing and outputting a signal, which will be described in detail with reference to FIGS. 2 to 6.

2 is a block diagram showing the operation of the processing apparatus with a 6-bit data signal as a 4-bit data signal in the digital signal processing apparatus of the present invention. As shown therein, 6-bit in the 6-bit analog / digital converter 11 is shown. The digital video signal, which is converted into a digital signal and outputted, is converted into a 4-bit digital signal by the digital signal processing apparatus 12 of the present invention and outputted to the digital signal.

That is, the present invention assumes that the 6-bit digital signals b ₀ to b ₅ (b ₁₀ to b ₁₅ ) are sequentially input from the analog / digital converter 11 in the digital signal processing apparatus 12. It is converted into a 4-bit digital signal b ₀ to b ₃ (b ₄ , b ₅ , b ₁₀ , b ₁₁ ) (b ₁₂ to b ₁₅ ), and then output to the memory 13 for storage.

On the other hand, Figure 4 is a detailed circuit diagram showing an embodiment of the digital signal processing apparatus of the present invention, as shown in the analog / digital to convert the input image signal to a 6-bit digital signal (b ₅ ~ b ₆ ) and output it A counter 110 for counting and outputting the input clock signal CLK to the output terminal Q, and inverting and outputting the inverted output terminal / Q, and the analog / digital converter 100; ), The digital signals b ₁ , b ₂ , b ₄ , b ₀ , b ₃ , and b ₅ are flip-flops F ₂ , F ₅ , F ₆ , F ₈ , F ₁₁ , and F ₁₂ . The digital signal b ₃ , b ₁ , b ₄ , b ₂ , b ₀ , b ₅ is flip-flop (F ₁ , F ₃ ) while being stored and output according to the signal of the output terminal (/ Q) of the 110. , F ₄ , F ₇ , and F ₁₀ store and output the digital signal separated output unit 120 and the output terminal of the counter 110 according to the signal of the output terminal (/ Q) of the counter 110. Q) Differentiate the signal Trigger signal consisting of capacitor (C ₁ ), resistor (R ₁ , R ₂ ), diode (D ₁ ), and buffer (BF) for shaping a rudder differential signal to generate a trigger signal in the rising section of the output terminal (Q) signal. The generator 130 and the mono vibrator 140 and 150 that are triggered according to the output signal of the trigger signal generator 130 to generate pulse signals having a width of 2 cycles and 4 cycles of a preset clock signal CLK. ), And inverts the output signal of the mono vibrator 140 to output the first control signal, and logically combines the output signal of the mono multi vibrator 140 and the output signal of the output terminal (/ Q). Outputting a control signal and shaping the output signal of the mono-multi vibrator 150 to output a third control signal, and exclusively inverting the output signal of the mono-multi vibrator 150 and the signal of the output terminal Q by Inverter outputting fourth control signal (IV ₁ to IV ₅ ), the control signal output unit 160 including the NOA gate NOR ₁ and the exclusive oragate EXOR, and first and third outputs from the control signal output unit 160. And a noar gate NOR ₂ to NOR ₅ and an inverter IV ₆ outputting one of the output signals of the flip-flops F ₁ to F ₃ as a second bit signal ID ₂ according to a fourth control signal. A third output signal of the flip-flops F ₄ to F ₆ according to the second bit signal output unit 170 and the second to fourth control signals output from the control signal output unit 160. The third bit signal output unit 180 including the NOR gates NOR ₆ to NOR ₉ and the inverter IV ₇ output as the bit signal ID ₃ , and the first signal output from the control signal output unit 160. And a noar gate NOR ₁₀ to NOR ₁₄ and an inverter IV outputting one of the output signals of the flip-flops F ₇ to F ₉ as a first bit signal ID ₁ according to the third and fourth control signals. ₈ , the first bit signal output unit 1 90 and outputting one of the output signals of the flip-flops F ₁₀ to F ₁₂ as a fourth bit signal ID ₄ according to the second to fourth control signals output from the control signal output unit 160. The fourth bit signal output unit 200 includes the NOR gates NOR ₁₄ to NOR ₁₇ and the inverter IV ₉ .

In the description of the drawings, reference numerals C ₂ and C ₃ , and VR ₁ and VR _P are capacitors and variable resistors for setting the time constants of the mono-multivibrator 140, 150.

In the digital signal processing apparatus of the image device of the present invention configured as described above, the counter 110 divides the clock signal CLK, which is input as shown in (a) of FIG. 5, into the output terminal Q. As shown in (b), the output is inverted and the inverted output terminal (/ Q) is output as shown in (c) of FIG. 5.

As such, the pulse signal output from the output terminal Q of the counter 110 is input to the trigger signal generator 130 and is divided by the differentiator of the capacitor C ₁ and the resistor R ₁ (d) of FIG. Differentiated as shown in FIG. 6, the plus differential signal is shaped through the diode D ₁ and shaped through the buffer BF, and then output as shown in FIG. 150 is input as a trigger signal.

Then, the mono-multi vibrator 140, 150 is triggered to have a width of two cycles and four cycles of the clock signal CLK respectively set by the capacitors C ₂ (C ₃ ) and the variable resistors VR ₁ (dVR ₂ ). The pulse signal is output as shown in (f) and (g) of FIG. 5, and the pulse signal output by the monomulti vibrator 140 is controlled through the inverter IV ₁ of the control signal output unit 160 through the fifth signal. As shown in (h) of FIG. 1, the signal is inverted and output as a first control signal. The signal of the inverted output terminal (/ Q) of the counter 110 and the inverted AND are combined at the NOR gate NOR ₁ and the inverter IV ₂ . Inverted at and outputted as the second control signal as shown in FIG.

In addition, the pulse signal output from the mono-multi vibrator 150 is inverted through the inverter IV ₃ of the control signal output unit 160 and inverted again through the inverter IV ₄ and is shown in FIG. 5 (j). As shown in FIG. 5, the signal is outputted as the third control signal and is exclusively ORed at the signal of the output terminal Q of the counter 110 and the exclusive oragate EXOR and inverted by the inverter IV ₅ . As shown in FIG. 4, the first to fourth control signals output from the control signal output unit 160 are input to the first to four bit signal output units 170 to 200.

Meanwhile, the input analog video signal is converted into the digital signals b ₀ to b ₅ by the analog / digital converter 100, and is output in synchronization with the clock signal CLK as shown in (l) of FIG. The digital signals b ₅ to b ₅ are applied to the input terminals D of the flip-flops F ₁ to F ₁₂ of the digital signal separation output unit 120 to be stored and output according to the output signal of the counter 110. do.

That is, the digital signals b ₁ , b ₂ , b ₄ , b ₀ , b ₃ , and b ₅ output from the analog / digital converter 100 are flip-flops according to the signal of the output terminal Q of the counter 110. (F ₂ , F ₅ , F ₆ , F ₃ , F ₁₁ , F ₁₂ ) are respectively stored and output to the first to fourth bit signal output units 170 to 200, and digital signals b ₃ , b ₁ , b ₄ , b ₂ , b ₀ , and b ₅ respectively correspond to the flip-flops F ₁ , F ₃ , F ₄ , F ₇ , F ₉ , and F ₁₀ according to the signal of the output terminal (/ Q) of the counter 110. It is stored and output to the first to fourth bit signal output units 170 to 200.

Then, the second bit signal output unit 170 may select one of the output signals of the flip-flops F ₁ to F ₃ according to the first, third and fourth control signals output from the control signal output unit 160. The second bit signal ID ₂ is output, and the third bit signal output unit 180 of the flip-flops F ₄ to F ₆ is generated according to the second to fourth control signals output from the control signal output unit 160. One of the output signals is output as a third bit signal ID ₃ , and the first bit signal output unit 190 is flipped according to the first, third and fourth control signals output from the control signal output unit 160. One of the output signals of the flops F ₇ to F ₉ is output as the first bit signal ID ₁ , and the fourth bit signal output unit 200 is second to fourth output from the control signal output unit 160. According to the control signal, one of the output signals of the flip-flops F ₁₀ to F ₁₂ is output as the fourth bit signal ID ₄ . Here, the operation of the first to fourth bit signal output units 170 to 200 will be described in more detail.

At the time t ₁ , as shown in FIG. 5B, the high potential is output from the output terminal Q of the counter 110, and the 6-bit digital signal outputted first by the analog-to-digital converter 100 ( b ₀ to b ₅ are stored and output in the flip-flops F ₂ , F ₅ , F ₆ , F ₈ , F ₁₁ and F ₁₂ of the digital signal separation output unit 120, as well as the control signal output unit 160. ), The first control signal is output at low potential as shown in (h) of FIG. 5, and the second to fourth control signals are all at high potential as shown in (i) to (k) of FIG. When output, the NOR gates NOR ₂ , NOR ₄ , NOR ₆ , NOR ₈ , NOR ₁₀ , NOR ₁₂ , NOR ₁₄ , and NOR _{16 of} the first to fourth bit signal output units 170 to 200 may have a high frequency. By the second to fourth control signals, all of the low potentials are independent of the output signals of the flip-flops F ₁ and F ₃ (F ₄ and F ₆ ) (F ₇ and F ₉ ) (F ₁₀ and F ₁₂ ). The NOR gate NOR ₃ , NOR ₇ , NOR ₁₁ , and NOR ₁₅ are flipped by the low-potential first control signal. Outputs the digital signals b ₁ , b ₂ , b ₀ and b ₃ output from the flops F ₂ , F ₅ , F ₈ , and F ₁₁ , respectively, and the noar gates NOR ₃ ( The output signal of NOR ₇ ) (NOR ₁₁ ) (NOR ₁₅ ) is Noah Gate (NOR ₅ ) (NOR ₈ ) (NOR ₁₃ ) (NOR ₁₇ ) and Inverter (IV ₆ ) (IV ₇ ) (IV ₈ ) (IV ₉ ) ) Are sequentially output as the second, third, first and fourth bit signals ID ₂ , ID ₃ , ID ₁ , and ID ₄ . In this state, the _second control signal output from the control signal output unit 160 at the time t ₂ becomes the low potential as shown in (i) of FIG. 5 and the first, the third and the fourth control. When the signals are all high potentials as shown in (h), (j) and (k) of FIG. 5, the noar gates NOR ₂ to NOR ₄ , are generated by the first, third and fourth control signals of the high potentials. NOR ₆ , NOR ₇ , NOR ₁₀ to NOR ₁₂ , NOR ₁₄ , and NOR ₁₅ all output low potential, and the noah gate NOR ₈ (NOR ₁₆ ) is flip-flop F by the second control signal of low potential. ₆ ) (F ₁₂ ) respectively outputs the digital signal (b ₄ ) (b ₅ ), and the output signals of the noah gate (NOR ₈ ) (NOR ₁₆ ) are the noah gate (NOR ₉ ) (NOR ₁₇ ) and Inverters IV ₇ and IV ₉ are output via respective ones.

In this state, at the time t ₃ , the high potential is output from the output terminal (/ Q) of the counter 110 as shown in (c) of FIG. 5 to be next output from the analog / digital converter 100. The 6-bit digital signals b ₀ to b ₅ are stored and output in the flip-flops F ₁ , F ₃ , F ₄ , F ₇ , F ₉ , and F ₁₀ of the digital signal separation output unit 120, respectively. In the control signal output unit 160, the fourth control signal is output at low potential as shown in (k) of FIG. 5, and the first to third control signals are shown in (h) to (j) of FIG. Likewise, when all of them are output at high potential, the noah gates NOR ₂ , NOR ₃ , NOR ₆ to NOR ₈ , NOR ₁₀ , NOR ₁₁ , and NOR ₁₄ to NOR ₁₅ all generate low potentials by the first to third control signals. The NOR gate NOR ₄ and NOR ₁₂ output the digital signals b ₁ and b ₀ respectively output from the flip-flop F ₃ and F ₉ by the fourth low-potential control signal. and NOR gate (NOR ₄₎ (NOR ₁₂₎ The output signal is output from each of the NOR gate (NOR ₅₎ (NOR ₁₃₎ and an inverter _{(IV 6) (IV 8)} .

In this state, at time t ₄ , the first, second, and fourth control signals are all output at high potential as shown in (h), (i), and (k) of FIG. When the signal is output at low potential as shown in (j) of FIG. 5, the noah gates (NOR ₂ , NOR ₄ ) (NOR ₇ , NOR ₈ ) (NOR ₁₁ , NOR ₁₂ ) (NOR ₁₅ , NOR ₁₆ ) By the second to fourth control signals, all of the low potentials are independent of the output signals of the flip-flops F ₂ and F ₃ (F ₅ and F ₆ ) (F ₈ and F ₉ ) (F ₁₁ and F ₁₂ ). The NOR gate NOR ₂ (NOR ₃ ) (NOR ₁₀ ) (NOR ₁₄ ) is flip-flop F ₁ (F ₄ ) (F ₇ ) (F ₁₀ ) by the first control signal of low potential. Output digital signals b ₃ , b ₄ , b ₂ , and b ₅ respectively, and the output signals of NOR gates NOR ₂ , NOR ₆ , NOR ₁₀ , and NOR ₁₄ are NOR gates. (NOR ₅ ) (NOR ₉ ) (NOR ₁₃ ) (NOR ₁₇ ) and Inverter (IV ₆ ) (IV ₇ ) (IV ₈ ) (IV ₉ ) are output respectively.

In this state, a high potential is output from the output terminal Q of the counter 110 at a time t ₅ , and a first control signal is output at a low potential from the control signal output unit 160. When all the control signals are output at high potential, the 6-bit digital signals b ₀ to b ₅ output from the analog-to-digital converter 100 are repeatedly performed from the operation of the time t ₁ to 4 bits and 2 bits. Will output separately.

That is, the subject innovation is an analog / digital signals from the digital converter _{(100) (b 0 ~ b} 5) (b 10 ~ b 15) the time as shown in Figure 6 on the assumption that sequentially outputs (t ₁ ) Outputs 4 bits of digital signals b ₀ to b ₃ of the first digital signals b ₀ to b ₅ to be outputted, and the remaining 2 bits of digital signals b ₄ to b _{15 at} time t ₂ . a power, and a time (t ₃₎ to the second output digital signal (b ₁₀ ~ b ₁₅₎ the digital signals of 2 bits (b _10, b ₁₁₎ an output, and the remaining 4-bit digital to time (t ₄₎ The signals b ₁₂ to b ₁₅ are outputted.

As described in detail above, the present invention divides the 6-bit digital signal output from the analog / digital converter into 4 bits and 2 bits, and outputs the 4-bit memory or 4 bit or 8 bit by simply converting the output digital signal into 4 or 8 bits. Since all the bits can be stored and output without remaining bits in the 8-bit memory, the use efficiency of the memory is improved.

Claims (3)

An analog / digital converter 100 that converts a video signal into a 6-bit digital signal b ₅ to b ₀ , and a clock signal CLK are counted and output to the output terminal Q, and an inverted output terminal (/ The counter 110 for inverting and outputting Q) and the digital signals b ₀ to b ₅ output from the analog / digital converter 100 are the signals of the output terminals Q and Q of the counter 110. And a digital signal separation output unit 120 for separately storing and outputting the data signal, a trigger signal generation unit 130 for generating a trigger signal in the rising section of the output terminal (Q) signal of the counter 110, and The monomultipliers 140 and 150 that are triggered according to the output signal of the trigger signal generator 130 to generate a pulse signal having a predetermined width, and the counter 110 and the monomultivibrator 140 and 150 A control signal output unit 160 for outputting first to fourth control signals according to an output signal of The digital signals b ₀ to b ₅ output from the output unit 120 are output according to the first, third, and fourth control signals output from the control signal output unit 160. The second bit signal output unit 170, the third bit signal output unit 180, and the first bit signal output unit 190 respectively outputting the fourth bit signals ID ₂ , ID ₃ , ID ₁ , and ID ₄ . And a fourth bit signal output unit (200). The control signal output unit 160 inverts the output signal of the mono multi vibrator 140 to output the first control signal, and outputs the output signal of the mono multi vibrator 140 and the output terminal ( / Q) outputs the second control signal by logical sum of the output signal, and outputs the third control signal by shaping the output signal of the mono-multi vibrator 150, and output signal and the counter ( And an exclusive inverted-OR of the output terminal (Q) signal of 110) to output a fourth control signal. The digital signal separation output unit 120 flip-flops the digital signals b ₁ , b ₂ , b ₄ , b ₀ , b ₃ , and b ₅ output from the analog / digital converter 100. (F ₂ , F ₅ , F ₆ , F ₉ , F ₁₁ , F ₁₂ ) store and output according to the output terminal (Q) signal of the counter 110, and the digital signals b ₃ , b ₁ , b ₄ , b ₂ , b ₀ , b ₅ ) are flip-flops (F ₁ , F ₃ , F ₄ , F ₇ , F ₉ , F ₁₀ ) stored and output according to the output terminal (/ Q) signal of the counter 110. The second bit signal output unit 170 outputs one of the output signals of the flip-flops F ₁ to F ₃ as a second bit signal ID ₂ according to the first, third and fourth control signals. The third bit signal output unit 180 may convert one of the output signals of the flip-flops F ₄ to F ₆ into a third bit signal according to the second to fourth control signals output from the control signal output unit 160. (ID _3), and outputs the first bit signal output section 190 has a first, third and fourth flip-flop in accordance with the control signal (F One of the output signals of ₇ to F ₉ is output as the first bit signal ID ₁ , and the fourth bit signal output unit 200 according to the second to fourth control signals has flip-flops F ₁₀ to F. ₁₂ ) A digital signal processing apparatus for a video device, characterized in that one of the output signal of the output as a fourth bit signal (ID ₄ ).