JP2783543B2 - Phase difference judgment circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a phase difference discriminating circuit for discriminating a phase difference between two signals.

(Prior Art) As a conventional phase difference discriminating circuit, for example, there is one as shown in FIG. As shown in FIG. 1, the phase difference discriminating circuit includes waveform shaping circuits 1a and 1b, an exclusive OR circuit 2, an integrating circuit 5 including a resistor 3 and a capacitor 4, and a comparator 6. A circuit A that outputs a phase difference between two input signals as a pulse signal is formed by the waveform shaping circuits 1a and 1b and the exclusive OR circuit 2.

The waveform shaping circuits 1a and 1b are connected to input terminals 11a and 11b,
The waveforms of the analog signals S1 and S2 input from the input terminals 11a and 11b are shaped, and rectangular wave signals S3 and S4 corresponding to the input analog signals are sent to the exclusive OR circuit 2. The exclusive OR circuit 2 takes an exclusive OR of the rectangular wave signals S3 and S4 input from the waveform shaping circuits 1a and 1b, and performs an integration circuit 5
Send to The integrating circuit 5 integrates the signal S5 output from the exclusive OR circuit 2 and outputs a signal S6 proportional to the pulse width.
Is generated and sent to the inverting input terminal of the comparator 6. The non-inverting input terminal of the comparator 6 is connected to a connection point 10 between the resistors 7 and 8, and the output terminal of the comparator 6 is connected via a resistor 9 to a connection point 10 between the resistors 7 and 8. Resistance 7
Is connected to a power supply Vs, and a voltage obtained by dividing the power supply Vs by resistors 7 and 8 is supplied to a non-inverting input terminal of the comparator 6 as a reference voltage Es. The reference voltage Es is a voltage corresponding to a phase difference to be a reference. The comparator 6 compares the output voltage of the integration circuit 5 with the reference voltage Es.
When the output voltage exceeds the reference voltage Es, the signal S7 is set to "1".

Next, the operation of the phase difference determination circuit will be described. FIG. 4 is a waveform diagram of signals at various parts of the phase difference discriminating circuit. Signals S1 and S2 shown in FIG.
When S2 is input, the waveform shaping circuits 1a and 1b shape the waveform of this signal and output rectangular wave signals S3 and S4 shown in FIG.

The exclusive OR circuit 2 takes the exclusive OR of the square wave signals S3 and S4 to generate a pulse signal corresponding to the phase difference.
Outputs S5. The integrating circuit 5 integrates the signal S5 and outputs a signal S6 proportional to the pulse width. The comparator 6 compares the signal S6 with the reference voltage Es. If the signal S6 obtained by integrating the pulse signal S5 corresponding to the phase difference exceeds the reference voltage Es, the signal
S7 is set to “1”.

When a phase difference occurs between the two signals S1 and S2, a signal S5 corresponding to the phase difference is output from the exclusive OR circuit 2,
When the integrated signal S6 exceeds the reference voltage Es corresponding to the phase difference to be used as a reference, the output signal S7 of the comparator 6 becomes "1".
It is determined that a phase difference has occurred between the signals S1 and S2.

However, in the conventional phase difference discriminating circuit, the integration constant of the integrating circuit 5, which converts the pulse signal S5 indicating the phase difference into a DC voltage proportional to the pulse width, is large in order to obtain a constant DC voltage without fluctuation. It is necessary to Therefore, it takes a long time from the occurrence of the phase difference in the input signal to the detection thereof. In addition, since the resistor 3 and the capacitor 4 have a large resistance value and a large capacity, the discrimination error increases, and the miniaturization of the entire phase difference discriminating circuit is hindered.

(Problems to be Solved by the Invention) As described above, the conventional phase difference determination circuit requires a long time to detect a phase change, has a large determination error, and has difficulty in downsizing the device. Had.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a phase difference discriminating circuit that has a short phase change detection time, has a small error in phase difference judgment, and is easy to downsize. It is in.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a circuit which outputs a phase difference between two signals as a pulse signal, and a circuit which is reset by the pulse signal and resets the pulse signal. A first counter that counts a high-speed pulse signal only when turned on and generates an output signal when a predetermined number is counted, and an output signal that is reset by an output signal of the first counter and counts the high-speed pulse signal and counts a predetermined number; A second counter; and a reset set flip-flop which is set by an output signal of the first counter and reset by an output signal of the second counter.

(Operation) In the present invention, when two signals are input, the phase difference between the signals is output as a pulse signal, and the first counter outputs the high-speed pulse signal only when the pulse signal is input and the pulse signal is on. When a high-speed pulse signal having a phase difference to be counted is counted, the output signal is turned on. When the output signal of the first counter is turned on, the reset set flip-flop is set and the output signal is turned on, so that it is determined that a phase difference has occurred between the two input signals.

The second counter is reset when the output signal of the first counter is turned on, and turns on the output signal when the high-speed pulse signal is counted and a predetermined number is counted. When the output signal of the second counter is turned on, the reset set flip-flop is reset. Therefore, if the output signal of the first counter does not turn on within a predetermined time, the output signal of the reset set flip-flop may be turned off. And return to the state.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of a phase difference determining circuit according to one embodiment of the present invention. In the figure, elements having the same functions as those of the conventional example shown in FIG. 3 are denoted by the same reference numerals, and redundant description will be avoided.

The phase difference determination circuit according to the present embodiment is a waveform shaping circuit 1a, 1
b, consisting of an exclusive OR circuit 2, a counter 21, a high-speed pulse signal generator 22, a switch 23, a counter 24, and a reset set flip-flop (RS flip-flop) 25.

The output signal of the exclusive OR circuit 2 is input to the reset terminal R of the counter 21. The clock input terminal CK of the counter 21 is connected to the high-speed pulse signal generator 22. The counter 21 is reset when the signal S5 is issued from the exclusive OR circuit 2, and counts the high-speed pulse signal S8 sent from the high-speed pulse signal generator 22 only when this signal S5 is "1". Output terminals Q ₁ , Q ₂ , Q ₃ ,
Output from the Q _4. The high-speed pulse signal generator 22 generates a high-speed pulse signal S8 and sends it to the counters 21 and 24. The switch 23 is connected to one of the output terminals of the counter 21 and sends an output signal S9 of the connected output terminal (Q _{3 in} the figure) to the counter 24 and the RS flip-flop 25. The counter 24 is reset by the signal S9, counts the high-speed pulse signal S8, and sends an output signal to the reset terminal R of the RS flip-flop 25. When the signal S9 input to the set terminal S becomes “1”, the output signal S11 becomes “1”, and when the signal S10 input to the reset terminal R becomes “1”, the output signal S11 becomes “0”. ".

Next, the operation of this embodiment will be described. FIG. 2 is a waveform diagram of signals at various parts of the phase difference discriminating circuit. Input terminal
When signals S1 and S2 are input to 11a and 11b, rectangular wave signals S3 and
S4 is output from the waveform shaping circuits 1a and 1b, and the exclusive OR circuit 2 outputs a pulse signal S5 according to the phase difference. The counter 21 is reset when the pulse signal S5 is input, and counts the high-speed pulse signal S8 only while the pulse signal S5 is "1" from the reset time. Since the switch 23 is connected to the output terminal Q _3, the pulse signal
S5 pulse width of only signal S9 when a certain level of the pulse width t ₁ becomes "1".

When the signal S9 becomes "1", the RS flip-flop 25 is set, the signal S11 becomes "1", and the two signals S1, S2
It can be seen that a phase difference has occurred.

When the signal S9 becomes "1", the counter 24 is reset, and the counter 24 counts the number of pulses of the high-speed pulse signal S8 from the reset time. The output signal of the counter 24 is output from the output terminals Q ₄ , Q ₅ , and Q _{6. In} this embodiment, the output signal S 10 of the output terminal Q ₅ is the RS flip-flop 2
5 is input to the reset terminal. For this reason, the counter 24 is reset by the output signal S9 of the counter 21 for a predetermined time.
When counting the t only ₂ minutes high speed pulse signal S8 signal S10 becomes "1". When the predetermined time t ₂ minutes before counting the high-speed pulse signal S8 signal S9 is "1", the counter 24 is reset again counts the high-speed pulse signal S8 from the time, high-speed pulse by ₂ minutes the predetermined time t When the signal S8 is counted, the signal S10 becomes "1" and the RS flip-flop 2
5 is reset, and the signal S11 becomes "0". Therefore, when the pulse width of the pulse signal S5 corresponding to the phase difference signal S9 becomes equal to or lower than the predetermined width can not become "1" within the predetermined time t _2, RS flip-flop 25 is reset, output signal
S11 returns to "0".

Thus, in this embodiment, the pulse signal corresponding to the phase difference
In determining the pulse width of S5, the number of high-speed pulse signals S8 as a reference is counted by the counter 21, and the count output is used for the determination output.
The determination error is also good. Further, since each circuit is constituted by a digital circuit, miniaturization becomes easy. In this embodiment, the pulse width t ₁ of the signal of the phase difference to be used as a reference can be appropriately selected by switching the switch 23, and the time t ₂ depends on the selection of the output terminal of the counter 24.
Settings can be changed.

[Effects of the Invention] As described above in detail, according to the present invention, it is possible to provide a phase difference discriminating circuit which has a short phase change detection time, has a small error in phase difference judgment, and can be easily miniaturized. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a phase difference discriminating circuit according to one embodiment of the present invention, FIG. 2 is a waveform diagram of signals of various parts according to the present embodiment, and FIG. FIG. 4 is a waveform diagram of signals of various parts of the conventional example. 1a, 1b… Waveform shaping circuit 2… Exclusive OR circuit 21… Counter 22… High-speed pulse signal generator 24… Counter 25… RS flip-flop

Claims (1)

(57) [Claims] 1. A circuit for outputting a phase difference between two signals as a pulse width of a pulse signal, a high-speed pulse signal is counted only when the pulse signal is reset and the pulse signal is on, and an output signal is counted when a predetermined number is counted. A first counter that emits, a second counter that is reset by an output signal of the first counter, counts the high-speed pulse signal, and emits an output signal when a predetermined number is counted, and is set by an output signal of the first counter. A reset set flip-flop reset by an output signal of the second counter.