JPS6029903B2 - frequency deviation detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency deviation detector that generates a DC output depending on the deviation between the frequency of an input signal and a set frequency.

Generally, a frequency deviation detector is used to automatically control the rotational speed of a rotating body.The frequency deviation detector extracts the deviation between the actual value and the set value of the rotational speed as a frequency deviation, and adjusts the operating unit so that this frequency deviation becomes zero. Used as an input element for the device.

Therefore, it is desired that this type of frequency deviation detector has relatively high detection accuracy and can suppress ripples to a minimum without impairing response speed. Conventionally, as this type of frequency deviation detector, one having a circuit configuration shown in FIG. 1 is known.

That is, the circuit shown in FIG. 1 includes an input terminal 10 and an output terminal 12, and a waveform shaping circuit 14 is connected between these terminals.
, Control circuit! 6, power supply circuit 18, filter amplifier 20,
It consists of a configuration in which switches 22, 23 and an inverting amplifier 24 are connected and arranged. The control circuit 16 includes a flip-flop 26, a reference oscillator 28, a gate 30, and a digital counter 32. However, the operation of the conventional frequency deviation detector configured as described above is as follows. Now, when an input signal having a frequency f is introduced into the input terminal 10', this input signal is converted by the waveform shaping circuit 14 into a pulse train having a period 1/f as shown in FIG. be done. Next, the output pulse obtained by the waveform shaping circuit 14 initially sets the flip-flop 26 of the control circuit 16 (the F side is in the ON state), and as a result, the control signal derived from the F side terminal of the flip-flop 26 2(b)], one switch 22 is closed, and a positive voltage of 10 V is supplied from the power supply circuit 18 to the input terminal of the filter amplifier 20 via the switch 22 (see FIG. 2(d)). At the same time, the gate 30 of the control circuit 16 is unlocked, and the digital counter 32 counts the pulses fo output from the reference oscillator 28 via the gate 30 until a preset count N is reached. When the digital counter 32 counts a predetermined count value N, it generates an output signal, and this output signal resets the flip-flop 26 (F2 side is on) and zeros the count content of the digital counter 32. Reset to . Due to this inversion operation of the flip-flop 26, [
2c], the switch 22 is closed and the switch 23 is opened, and the negative voltage -V is supplied from the power supply circuit 18 to the input device of the filter amplifier 20 via the inverting amplifier 24 and the switch 23. [See Figure 2d]. Thereafter, each time a pulse train with a period of 1'f is supplied from the waveform shaping circuit 14 to the flip-flop 26 of the control circuit 16, the above operation is repeated, and the input terminal of the filter amplifier 20 receives a signal as shown in FIG. 2d. A voltage having a waveform will be input. Therefore, at the output end of the filter amplifier 20, that is, at the output terminal 12, a DC output Eo having a polarity and a magnitude depending on the deviation between the frequency f of the input signal and the set frequency.
is taken out. However, since the conventional frequency deviation detector configured in this way outputs a rectangular wave voltage as shown in FIG. 2d through a filter amplifier, there is always ripple in its DC output. Moreover, in order to make this ripple as small as possible, there is a drawback that the response speed must be made constant.

Therefore, as a result of various studies to overcome all the problems of the conventional frequency deviation detector mentioned above, the inventors of the present invention decided to replace the filter amplifier in the conventional frequency deviation detector with two sets of integrators. Analog switches and sample-and-hold circuits corresponding to these integrators are provided, and each integrator performs an integral operation and holds and sets the integral value alternately every predetermined cycle of the input signal, and each analog By configuring the output of each integrator to be sampled and held in a sample-and-hold circuit via a switch and output, the signal has a polarity and magnitude that depend on the deviation between the frequency of the input signal and the set frequency for each period of the input signal. Moreover, it has been found that it is possible to obtain a DC output that does not contain any ripples, and that the above-mentioned problems can be solved at once.

Therefore, an object of the present invention is to provide a highly accurate frequency deviation detector that does not impair response speed and does not include any ripples.

In order to achieve the above object, in the present invention, an input signal having an unknown frequency is processed by inputting an input signal having the same frequency and having a predetermined polarity pulse period having a constant time width and a magnetic pulse period having the remaining time width. In a frequency deviation detector configured to convert into a pulse signal and obtain from the pulse signal a DC signal having a polarity and magnitude depending on the deviation between the frequency of the input signal and a set frequency, two integrators that integrate the pulse signal in a cycle, and sample the output of one of the integrators within the predetermined magnetic pulse period during the integration operation cycle of the other integrator before setting the other integrator. A predetermined time width of a positive voltage and a negative voltage generated for each pulse period in correspondence with each integrator between a sample hold circuit that holds the DC signal and outputs it as the DC signal, and the two integrators and the sample hold circuit. The invention is characterized in that it is provided with an analog switch that is controlled based on a signal that defines the.

Next, embodiments of the frequency deviation detector according to the present invention will be described in detail below with reference to the accompanying drawings.

For convenience of explanation, the same reference numerals are given to the same components as those of the conventional frequency deviation detector shown in FIG. 1, and detailed explanation thereof will be omitted. FIG. 3 is a circuit diagram showing an embodiment of the frequency deviation detector according to the present invention. That is, the circuit of this embodiment is configured to supply the output signal of the control circuit 16 to the switches 22 and 23 via the JK flip-flop 34 and the AND circuit 36. Also,
As a DC output circuit, a pair of integrators 38 and 40 and these integrators 38 are used instead of two conventional filter amplifiers.
, 40 and corresponding analog switches 42, 44, and these integrators 38, 40 and analog switches 42, 44.
a control circuit 46 that controls the sample and hold circuit 48;
It has been established that The other circuit configuration is exactly the same as the conventional circuit shown in FIG. Next, the operation of the circuit of the present invention configured as described above will be explained with reference to the operation waveform diagram shown in FIG.

Now, when an input signal having an unknown frequency f is introduced into the input terminal 10, this input signal is converted by the waveform shaping circuit 14 into a pulse train having a period 1'f as shown in FIG. 4a. .

Next, the output pulse obtained by the waveform shaping circuit 14 sets the flip-flop 26 of the control circuit 16 in the set state (F,
F, F of this flip-flop 26
By the AND condition of the control signal derived from the side terminal and the output signal of the JK flip-flop 34, the AND circuit 3
A control signal is output from the switch 6 [see FIG.
A positive voltage of 10 V is supplied to the input terminal of one of the integrators 38 via the integrator 2. In this case, the integrator 38 integrates the input voltage in the negative direction with a preset integration time constant, as shown in FIG. 4d. At the same time, the gate 30 of the control circuit 16 is unlocked, and the digital counter 32 controls the pulse fo output from the reference oscillator 28 through the gate 30 until it reaches a preset count value N. Count. Then, the digital counter 3
2 generates an output signal when a predetermined count content N is counted, and this output signal resets the flip-flop 26 (F2 side is on), resets the count content of the digital counter 32 to zero, and further J
The state of the 1K flip-flop 34 is reversed. As a result, the control signal output from the AND circuit 36 [Fig.
], one switch 22 is closed and the other switch 23 is closed, and the input terminal of the integrator 38 is supplied with a negative voltage - V is supplied. In this case, the integrator 38 integrates the input voltage in the positive direction with a preset integration time constant, as shown in FIG. 4d. Then, the integrator 38 outputs the next pulse from the waveform shaping circuit 14 and the flip-flop 26 is set to the set state (F
, is on), and after 1'f period, the flip-flop 26 is reversed, the gate 30 is unlocked again, and the digital counter 32 outputs the pulse fo output from the reference oscillator 28. It starts the hold state as soon as it starts counting, and resets after a certain period of time. In this way, when the output of the integrator 38 is held, the analog switch 42 starts sampling and holds that state until the output of the integrator 38 is reset (see Figure 4 f). ], during this period, a DC output Eo is outputted via the sample and hold circuit 48 (see FIG. 4h). In addition, in this embodiment, when the second pulse is output from the waveform shaping circuit 14 and the flip-flop 26 becomes set state (F side is on state), the input terminal of the other integrator 40 is A positive voltage +V and a negative voltage -V are alternately supplied from the power supply circuit 18 to perform an integrating operation, and then the output of the integrator 40 is held [see FIG. 4e], and the analog switch 44
performs sampling [see FIG. 4g], and a DC output Eo is outputted via the sample-and-hold circuit 48 [see FIG. 4h].

The operating points of the integrators 38 and 40 and the analog switches 42 and 44 described above are controlled by a control signal from an AND gate 36 via a control circuit 46.

According to the circuit of this embodiment, while the integrator 38 or 40 is performing an integrating operation, its output is integrated with the same slope in the negative direction and the positive direction, so that the unknown frequency f of the input signal is preset. If the frequency is different from the calculated frequency, it is integrated to a value proportional to the difference, and sampled and held by the sample and hold circuit 48.

Therefore, at the output terminal 12, the frequency f of the input signal is
and has a polarity and magnitude depending on the deviation of the set frequency,
Moreover, a DC output Eo containing no ripple can be extracted. In particular, the frequency deviation detector according to the present invention includes:
By providing two sets of integrators and corresponding analog switches and sample-and-hold circuits in place of the conventional filter amplifier, each integrator can be used for each period 1/f of the pulse train output from the waveform shaping circuit. The output of each integrator is sampled and held alternately every 1/f period by integrating, holding, and resetting alternately, and the frequency deviation can be extracted for each period of the frequency of the input signal without including ripple. Moreover, it has excellent characteristics such as quick response characteristics. Therefore, according to the present invention, the accuracy and reliability of this type of frequency deviation detector can be significantly improved. Although the preferred embodiments of the present invention have been described above, it goes without saying that various design changes can be made without departing from the spirit of the present invention.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional frequency deviation detector, Figure 2 a~
d is an operating waveform diagram of the circuit shown in FIG. 1, FIG. 3 is a circuit diagram of a frequency deviation detector according to the present invention, and FIGS.
FIG. 3 is an operation waveform diagram of the circuit shown in the figure. 10... Input terminal, 12... Output terminal, 14... Waveform shaping circuit, 16... Control circuit, 18... Power supply circuit, 20... ... Filter amplifier, 22, 23 ... Switch, 24 ... Inverting amplifier, 26 ... Flip-flop, 28.
...Reference oscillator, 30...Gate, 32
...Digital counter, 34...J-K flip-flop, 36...AND circuit, 38, 40...Integrator, 42, 44...Analog switch, 46
......control circuit, 48...sample hold circuit. FIG. IFIG. 2 FIG. 3 FIG・mu

Claims (1)

[Claims] 1. Convert an input signal having an unknown frequency into a pulse signal having the same frequency and consisting of a pulse period of a predetermined polarity with one cycle having a constant time width and a pulse period of the other polarity with the remaining time width, and input from that pulse signal. In a frequency deviation detector configured to obtain a DC signal having a polarity and magnitude depending on the deviation between the frequency of the signal and a set frequency, two an integrator; and a sample hold for sampling and holding the output of one integrator within the predetermined polarity pulse period during the integration operation cycle of the other integrator and outputting it as the DC signal. an analog switch that is controlled based on a signal defining a predetermined time width of a positive voltage and a negative voltage generated in each pulse period in correspondence with each integrator between the circuit, the two integrators and the sample-and-hold circuit; A frequency deviation detector comprising: